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Last Monday was the TSMC Technology Summit 2020. Virtual, of course. I covered that in my post TSMC Technology Symposium: All the Processes, All the Fabs. Today it is the turn of specialty processes and advanced package, for which TSMC now uses the name 3DFabric.
Kevin Zhang presented the specialty technology portfolio. This covers everything except the main line of digital process nodes. One amazing thing about TSMC is that they have never closed a fab. Old TSMC fabs don't die, they become specialty technology fabs. The segment has been growing fast with a CAGR of 17%, going from 2.5M wafers in 2009 to 12.7M wafers last year. The range is staggering. They have 270 different specialty technologies, used to manufacture 10,000 products for 500 different customers.
That's a lot of technologies, as you can see from the above picture, and you'll be glad to know that Kevin didn't attempt to cover them all. He focused on four areas:
The latest and greatest ultra-low-power process doesn't have the usual ULL process designation, it is N12e. As you would guess, this is related to the N12 digital process, which is a shrink of N16FFC. The previous generation of ultra-low-power was at N22 (a shrink of N28).
The above table shows the improvement at N12e versus 22ULL. There is also an ultra-low-leakage SRAM with >50% reduction in retention current. They have also reduced leakage in general by over 10% with a new device. Voltage goes down below 0.4V. Risk production for N12e started in 1Q 2020.
FinFET has some intrinsic limitations for RF due to its high gate capacitance. However, with an innovative device, TSMC has achieved up to 400GHz based on N16 FinFET. At N6, they can bring much more compute function onto the same die, although that is in the future. The 0.1 version of the SPICE model is targeted for Q2 2021. The process is called N6RF. The 5.8GHz frequency is significant since that is the main (so-called sub-6GHz) band of 5G (but mmWave is more like 25GHz, a lot higher frequency).
ESF3 is TSMC's latest eFlash technology based on 28HPC+. It will be qualified for automotive by the end of this year.
But 28nm is the end of the line for flash since the floating-gate technology used doesn't really work. Dedicated flash solved that issue by going 3D, but for embedded memory, that is clearly not economically feasible. Instead, there is RRAM (resistive RAM) and MRAM (magneto-resistive RAM). Both of these are built in the metal stack, and TSMC has both technologies available in N40 and N22. MRAM is targeted for N16 at the end of next year for eFlash-like and the end of 2022 for RAM-like.
These technologies don't depend on floating gates. RRAM depends on a resistive filament being present or absent, and MRAM depends on changing the magnetic field direction and sensing that by a change in resistance. As I heard someone say recently, "for the last ten years I've been talking about these technologies as emerging...well, I'm pleased to say that they have emerged".
CMOS image sensor (or CIS) is important for smartphone cameras and also for autonomous driving cameras. As you can see, in the last decade there has been a 20X increase in resolution from 5 megapixels to over 100 megapixels. To achieve that, some come from making larger sensors. But also the pixel size has reduced from 1.75um to under 0.6um.
Doug Yu presented TSMC's advanced packaging roadmap, now all grouped under a new name 3DFabric. Until now, TSMC's advanced packaging has been under the names InFO (for integrated fanout) and CoWoS (for chip on wafer on substrate). More recently they have had SoIC, systems on integrated chips (also called chip-stacking), which is further subdivided into CoW and WoW (chip on wafer and wafer on wafer). These technologies have been used in over 100 products. InFO and CoWoS are also subdivided depending on the type of interposer and the type of routing (if any).
SoIC allows chips to be stacked with bumpless interconnect. This allows you to get signals on one chip as close as possible to signals on another (compared to side by side on an interposer, for example). There is a lot of flexibility about how the chips are interfaced and manufactured, with face-to-face (F2F) and face-to-back (F2B) supported, along with chip-on-wafer (CoW), wafer-on-wafer (WoW), and lots more acronyms all supported. There is a roadmap to reduce the TSV pitch from 9um today to 4.5um in 2023 (the TSMC slide says "mm" but I'm sure they mean "um").
Here's a test vehicle that they built. This is 12 stacked die thinned so that the total thickness is less than 600um.
The next technology that Doug talked about was InFO-R/oS for chiplet integration on a substrate. The substrate can be bigger than the maximum reticle size (1.5X since 2018, 1.7X later this year, 2.5X by Q1 2021). There is 2um x 2um RDL.
InFO-L/LSI is for ultra-high bandwidth systems. L stands for local interconnect, higher density than the InFO-R family. Qual should be complete by Q1 2021.
There is a whole roadmap for CoWoS-S for HPC (and -L adding local interconnect, and other variants...too many to keep up with!).
Doug introduced STAR, for STandard ARchitecture. This is aimed at integrating HBM2 (STAR 1.0) or HBM 2E (STAR 2.0).
Finally, all these technologies can be combined together using front-end 3D integration, back-end 3D integration, SoIC, and InFO for mobile.
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