Get email delivery of the Cadence blog featured here
This Wednesday was TSMC's OIP Ecosystem Forum, one of two major events that TSMC run each year. The stars of the OIP Symposium are not so much TSMC themselves but their partners, one of whom is Cadence. We presented six papers during the day, and had our expert bar in the exhibit hall during the breaks. During the last few days, we have put out many TSMC-related press releases: the CCIX test chip, 7nm and 7nm FinFET+, 12FFC, automotive IP on 16FFC, and TSMC's 3D packaging technologies CoWoS and InFO (even the names are three dimensional with the careful mix of upper and lower-case letters).
The most important presentation of the day is the process roadmap update. TSMC generally does not publish much of this data on their website or anywhere else. In fact, the only way you can find most of this out (apart from being one of their big customers) is at the two big events each year, the Technology Symposium in the early part of the year, and at the OIP Forum in the fall. There are international versions of both events, too. As always, I preface my post with a caveat: TSMC doesn't hand out the slides of the presentation, and doesn't allow photography, video, or recording. So this is entirely from my notes and may contain minor errors. But you won't find this information anywhere else.
The presentation was given by Cliff Hou, who is VP R&D for the Design and Technology Platform. Historically, until a few years ago, TSMC used mobile as their technology driver and other markets had to make do with whatever resulted from that. As the growth in mobile has slowed, TSMC is focusing on four segments with special technology options: mobile (still), high-performance computing (HPC), automotive, and IoT.
The main processes for each segment are:
Below, I will give more details of the processes for each segment: performance, production roadmap, and so on.
N7 process qual is completed and risk start has commenced. The entire EDA flow is exercised and validated. Foundation IP is ready. Ecosystem IP already has some silicon validation. There have been multiple tapeouts already, with over 10 expected by the end of the year. Volume production starts in the first half of 2018.
N7+ is the second-generation 7nm process. It has 1.2X logic density of N7, 8-20% higher speed (at same power) or 15-20% lower power at the same speed. EUV is used on critical layers. The design rules are slightly different for EUV versus 193i, but TSMC has created a migration utility to automate design porting. The effort to port IP is "less than that from v0.5 to v1.0 was".
Compared to 16FFC, N7 has a 33% speed increase or a 58% power reduction. Going from N7 to N7+ gets another 7% speed gain or another 16% power reduction.
12FFC is a fast PPA upgrade from 16FFC. It is an optical shrink. However, there is also a new 6T standard cell library, that pushes density up 1.2X vs the 7.5T library on 16FFC. v0.1 DRM/SPICE is issued. The V1.0 EDA certification is completed. The IP portfolio is recharacterized and revalidated. The PPA numbers have been confirmed with a customer design.
There are 10 tapeouts expected in 12FFC by the end of the year.
There are a number of features in the process specially aimed at HPC. In FEOL, there is over-drive and a larger CPP (contacted poly pitch). BEOL has wide metal, large vias, and via pillars.
On the IP front, there is an H300 standard cell library using the larger CPP, cache macros for L1, L2, L3, high-speed SerDes, low-jitter ADPLL, and a HBM2 (high bandwidth memory) PHY.
There are additional features in Innovus to use the via pillar, to build low-IR/EM power grid and low-skew clock nets.
TSMC just taped out an N7 HPC TV chip with a 4GHz ARM Cortex-A72. They will get silicon at the end of the year. Cliff promised to update us at the TSMC Technology Symposium early next year.
He also talked about the Cadence/Xilinx/ARM/TSMC CCIX demonstrator. For more details on this, see my post Xilinx/Arm/Cadence/TSMC Announce World's First 7nm CCIX Silicon Demonstrator.
Several existing processes are particularly appropriate for IoT, namely 55ULP, 40ULP, 28HPC+, and 16FFC.
Two new processes are 22UPP and 22ULL. These are 5% optical shrink from 28HPC+, with a new photo resist and litho/etch integration. It supports 0.6V operation. Compared to 28HPC+, there is a 15% speed increase or a 30% power decrease, along with a 10% area benefit.
There are enhanced RF and analog features for 5G, mmWave, and connectivity. A new high bandwidth device achieves greater than 400GHz, 1/f noise improved 2X, new high voltage for embedded PMIC at 6.5V.
For the 22nm processes, SPICE will be ready in Q4, foundation IP early next year (since it is an optical shrink, the design rules are basically unchanged from 28nm apart from scaling).
Automotive requires additional software, and additional qualification using a wider temperature range than mobile in order to achieve the quality, functional safety, and reliability required. Basically, it extends the 16FFC mobile technology to automotive grade. ASIL-B is used for IP architecture and ASIL-D for IP development. EDA tool confidence-level assessment and classification is also required.
The 3D packaging technology InFO (integrated fan-out) will have the InFO_MS design flow ready August 2018 to support logic die and memory die integrated together in the same package.
Wafer on wafer (WoW) design flows will be ready February 2018.
TSMC has been developing machine learning approaches to drive Innovus/Genus solutions in order to boost performance, reduce area, and optimize productivity One example is that they achieved 8-12% synthesis performance gain via fine-grained path groups identified using machine learning. They can also achieve 3% smaller area at the same time, while reducing the number of DRC violations from 6000 to 800, so also improving productivity.
Mentor's Wally Rhines wins the prize for best joke of the day. He pointed out how marketing is underrated, but they have done as much as anyone to increase TSMC's yield. In the old TSMC logo on the left below, there are over 20 bad die (inked in black during wafer test). But by the time of the new logo, marketing had got the defects down to 11.
Click the image below for the latest Breakfast Bytes...
Sign up for Sunday Brunch, the weekly Breakfast Bytes email.