TSMC OIP: N3E/N4P, 3DFabric, Analog Migration

Today, it ia TSMC's OIP, the Open Innovation Platform Ecosystem Forum. I will write about some of what was said there soon. But in the meantime, as usual, Cadence has made several announcements jointly with TSMC.

N3E and N4P Node Certification

The first thing that we always announce is support for TSMC's latest nodes. Today, we are announcing support for N3E and N4P. This includes support for FinFLEX technology, which is TSMC's capability to vary the number of fins on transistors, in particular, having a different number of fins on the P and N transistors (see the diagram below).

The Cadence tool portfolio for both the digital full-flow and the custom/analog flow are both certified on both nodes. I'm not going to give you a complete list of all the tools; I write about them all the time. As always, the basic message is that all TSMC processes, including the most advanced ones, are supported by all Cadence tools (apart from inapplicable ones like PCB and RF). But for RF, see below in this post.

Integrity 3D-IC Certified on All TSMC 3DFabric Offerings

Integrity 3D-IC was announced earlier this year. See my post Introducing the Integrity 3D-IC Platform for Multi-Chiplet Design for details. Integrity 3D-IC is now certified on all TSMC 3DFabric offerings. This means:

• InFO Integrated fanout
• CoWoS Chip on Wafer on Substrate
• SoIC System on Integrated Chips
• 3Dblox

I'm not sure what 3Dblox is. Perhaps it will be made clear at OIP. Here's a quote from the press release:

As part of the collaboration, the companies worked together to develop TSMC’s latest 3Dblox technology and Cadence’s Advanced Substrate Router (ASR) to help customers accelerate advanced multi-die package design.
...
3DBlox streamlines key aspects of design methodologies and allows chiplet reuse, providing a seamless interface for Cadence system analysis tools for early power delivery network (PDN) and thermal analysis

Custom/Analog Process Migration Flow

Cadence's new flow is built on top of what I believe is our oldest product, or at least oldest product name, Virtuoso. The new flow enables node-to-node design migration for custom/analog blocks that use TSMC's advanced process technologies. We worked jointly with TSMC's R&D teams. to ensure that Virtuoso Schematic Editor and Virtuoso Layout Editor automatically migrate a source design on TSMC's N5 and N4 process technologies to create a new design on TSMC N3E technology. Early trials of the technology showed that the migration time was more than 2.5X as fast as a manual approach.

In a little more detail:

The Virtuoso Application Library Environment schematic migration solution, which is integrated into the Virtuoso design platform, automatically migrates a source schematic’s cells, parameters, pins and wiring from one process node to another technology. The target schematic is then tuned and optimized using the Virtuoso ADE Product Suite’s simulation environment and circuit optimization technology to verify the new schematic meets all necessary measurement targets.  

The Virtuoso Layout Suite supports the reuse of existing layouts on a given process technology to quickly recreate a migrated layout on a new process technology, using custom place and route automation. Thanks to Virtuoso Layout Suite templates, TSMC’s analog-mapping technology and the routing technology in the Virtuoso design platform, designers can automatically recognize and extract groups of devices in an existing layout and apply templates to similar groups in the new layout.

UPDATE: TSMC N16 mmWave Reference Flow

Later in the day, Cadence announced the N16 mmWave Reference Flow work.

First, a quick primer. Oversimplifying, 5G operates in two bands, known as sub-6GHz and mmWave. The sub-6GHz obviously operates in the usual cellular frequencies used for 4G and earlier. But mmWave operates over 24GHz and requires a different RF design flow. For more details, see my posts What Is 5G? and Why Is 5G Such a Big Deal?

Today, we announced that Cadence's RFIC solutions support TSMC's N16RF Design Reference Flow and PDK to allow mutual customers to design with Cadence solutions for TSMC’s N16RF mmWave semiconductor technology.

Taking a look under the hood:

The complete RF Design Reference Flow includes passive device modeling, block-level optimization, sensitive layout routing nets EM parasitics signoff, EM-IR analysis with custom passives, and self-heating. The reference flow features several products optimized for TSMC’s N16RF mmWave process technology, including the Cadence Virtuoso Schematic Editor, Virtuoso ADE Product Suite, and integrated Spectre X Simulator and RF option. Additionally, the flow features high capacity electromagnetic (EM) model generation using the Cadence EMX 3D Planar Solver for seamless back-annotation of S-parameter models into golden schematic and EM-IR analysis with self-heating with the Voltus-Fi Custom Power Integrity Solution, allowing automatic management of EM and RCX models for RF-accurate results. The flow enables users to effectively manage corner simulations and achieve design robustness. The EMX Planar 3D Solver and Quantus Parasitic Extraction are integrated into the Virtuoso platform, enabling layered extraction of coupling effects and guaranteeing full-design EM parasitic signoff. The Cadence RFIC full flow offers an efficient methodology that lets engineers achieve design goals—performance, power efficiency and reliability—in a single, tightly integrated design environment.

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