Countdown to TSMC Technology Symposium: 7nm, 5nm, 3nm, June 1

Today it is the TSMC 2021 Online North America Technology Symposium (tomorrow for China, Europe, Taiwan). Usually, I do a preview post about what is coming up and what is on the agenda, but last week was just too crowded with Cadence announcements (some with TSMC) on Monday, Tuesday, Wednesday. Then on Thursday, I had to preview our own CadenceLIVE since that is also imminent (June 8 and 9...see my post for more details) even though we were also announcing the joint work that we have been doing with TSMC on N4 and N3. But better late than never, so more on that below.

TSMC N4 and N3 with the Cadence EDA Tools

I don't usually quote directly from press releases, but in this case I think it is wise since I don't want to say or imply more than we are actually announcing. Today Cadence announced:

that it is expanding its collaboration with TSMC to accelerate mobile, AI and hyperscale computing application design using the integrated digital flow and custom/analog tool suite on TSMC’s N3 and N4 process technologies. Joint Cadence and TSMC customers have already successfully used the digital and custom/analog tools to complete test chip tapeouts. As part of the collaboration, the Cadence digital and custom/analog tools have been optimized and certified for TSMC’s N3 and N4 process technologies, supporting the latest Design Rule Manual (DRM) certification and SPICE correlation. The corresponding N3 and N4 process design kits (PDKs) are available now.

There are lots more details of the flows in the press release, but I like to summarize the situation as the entire Cadence digital and custom/analog tools support all TSMC process nodes down to N3 (3nm), tapeouts of test chips have taken place, and PDKs are available. So if you want to do an N4 or N3 design, go for it! And, of course, other processes are available.

TSMC Technology Symposium

The main reason to attend the Technology Symposium is that this is one of only two occasions per year (the other being the OIP Ecosystem Forum in the fall) when the company lays out details of its process roadmaps, process timetables, fab construction, and so on. This information is not generally available simply by looking around the TSMC website. I will be attending, and I will summarize some of the most important details in some future blog posts, but obviously I cannot condense an entire day of presentations into a few thousand words.

The event will start at 9:30am Pacific Time with a keynote by TSMC's CEO C.C. Wei with invited guests.

There is no detailed schedule for the rest of the day, but the order that the other presentations are billed on the TSMC website is:

• Advanced Technology Leadership / Design Solution and Enablement by Y.J. Mii, SVP, R&D
• Specialty Technology Leadership by Kevin Zhang, SVP, BD
• Manufacturing Excellence by Y.P. Chin, SVP, Operations
• Advanced Technology for Smartphone & HPC Platforms by Yujun Li, Director, HPC BD
• 3DFabric Technology by Jerry Tzou, Director, Advanced Packaging BD
• Ultra-Low Power Technology for IoT Platform by Simon Wang, Senior Director, IoT BD
• BCD Technologies for PMIC by Lin Wu, Director, Power Management and Display IC BD
• eNVM & Automotive by Cheng-Ming Lin, Director, Automotive & MCU BD
• Advanced RF and Analog Technology by Jie Jay Sun, Director, RF and Analog BD

Learn More

Here is the TSMC webpage that covers the symposium. I assume you can still register at the last minute here, too.

As I said above, I will attend the Technology Symposium and you can expect coverage of the key announcements in blog posts coming up in the next couple of weeks. Watch this space, as newspapers used to say back when people still read newspapers on paper.

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