Breakfast Bytes Blogs

Most conferences take place annually, or in some cases every two years. The History of Programming Languages (HOPL) is held more like once every fifteen years. The first three were held in 1978, 1993, and 2007. The fourth was going to be held last year. One advantage over annual conferences is that it is no big deal to postpone it for a year, which is what they did, in the hopes that it would not need to be virtual. But that hope did not pan out. HOPL IV will be virtual and held Sunday, June 20, through Tuesday, June 22, 2021.

To give you a flavor of the conference, here are three of the papers in HOPL IV. If you know about the roots of these languages, you will recognize the names of most of the authors:

• Thriving in a Crowded and Changing World: C++ 2006-2020 by Bjarne Stroustrup
• JavaScript: The First 20 Years by Allen Wirfs-Brock and Brendan Eich
• A History of MATLAB by Jack Little and Cleve Moler

The papers at HOPL IV are listed in alphabetical order of the language, starting with APL and ending with...Verilog. The alphabetically last paper is Verilog HDL and its Ancestors and Descendants by Peter Flake, Phil Moorby, Steve Golson, Arturo Salz, and Simon Davidmann. You probably recognize some of these names, at least Phil Moorby. While at Gateway Design Automation, Phil created the Verilog language and its simulator Verilog-XL. Cadence acquired Gateway in 1989. He received the 2005 Phil Kaufman award for the invention of Verilog, and in 2016 was made a Fellow of the Computer History Museum. I attended the dinner at the CHM associated with his induction as a fellow. You can read about that in my post Phil Moorby and the History of Verilog.

The full text of the paper is here. Note that it is 90 pages long before you casually print it. Yes, many of the papers at HOPL are long, over 100 pages even (the C++ paper is 168 pages). All the papers from this year's HOPL IV are publicly available on this page. The abstract of the Verilog paper is:

This paper describes the history of the Verilog hardware description language (HDL), including its influential predecessors and successors. Since its creation in 1984 and first sale in 1985, Verilog has completely revolutionized the design of hardware. Verilog enabled the development and wide acceptance of logic synthesis. For large-scale digital logic design, previous schematic-based techniques have transformed into textual register-transfer level (RTL) descriptions written in Verilog. As of 2018 about 80% of integrated circuit design teams worldwide use Verilog and its compatible descendant SystemVerilog.

The main predecessor of Verilog was HILO, developed at Brunel University (which is in Uxbridge, near Heathrow Airport to the West of London). I was doing research for a PhD at the University of Edinburgh. However, like many PhD students, I didn't completely stick to working on my thesis topic (distributed file systems) and I did a fair bit of work on EDA (although we called it Computer-Aided Design, or CAD, in those days). For my career, that turned out to be more important. At one point, a group of us visited Brunel University to discuss CAD in general, and HILO in particular. Simon and I would work together at Ambit about twenty years later. We've not been able to work out whether we met at Brunel that day or not, nor whether I met Phil or Peter either.

Simon, Phil, and Peter got the band back together again to create Co-Design Automation where they created Superlog. Synopsys acquired Co-Design in 2002. The language became SystemVerilog and eventually became IEEE standard 1800.

DVCon

DVCon took place in the first week of March, and Simon's company Imperas sponsored a session called A Personal Perspective on the History of SystemVerilog, with Simon, Peter Flake, and Phil Moorby. That's the three of them in the photo from forty years ago, around the time of my visit to Brunel University. Yeah, I looked a lot younger, too.

The diagram below shows the timeline of the Verilog family tree. The biggest influence was HILO, and in fact some reserved words from HILO remain as reserved words in SystemVerilog nearly 50 years later. Vera was developed in parallel to Verilog, and along with SuperLog (developed at Co-Design Automation) fed into what became SystemVerilog. Verilog itself went through various versions from Gateway's proprietary version, then at Cadence, and eventually OpenVerilog and the IEEE 1364 standard. Today, what we see in SystemVerilog has been nearly fifty years in the making.

Peter (pre-Verilog)

HILO 1 project started in 1972 at Bradford University and then later moved to Brunel University. It was intended for both design verification but especially test development. Remember, this was the age of MSI integration, not integrated circuits, so "simulation" was often simply done by building a breadboard. It was test that was the big issue, especially given the very limited computer power available in the early 1970s (just 32K words of core memory, for example). HILO 1 had a simple view of the world, with unidirectional wires, and binary logic values. It was a unit delay simulator without timing. It was written in assembly code, and supported serial fault simulation for test development.

HILO 2 was a complete re-write in BCPL (a forerunner of C and C++ that was the main language used in the Cambridge University Computer Laboratory when I was an undergraduate), starting in 1977 at Brunel. The British Ministry of Defence (MoD) had liked HILO 1 and basically funded this redesign. It had bi-directional wires and ports, four logic values, and delays and timing checks. It had named events, which exist in Verilog and SystemVerilog.

HILO 3 supported parallel fault simulation for test development, using all 32 bits of the word do simulate 31 faults together. GenRad marketed the product, and one of the first bits of customer feedback was the need for logic strengths (15 value implementation added in 1983). HILO 3 was implemented in C and was a reasonable commercial success in the 1980s. The basis of the success was people writing models in the hardware description language, whereas people doing ASIC designs were mostly still doing schematic capture.

Phil (Verilog)

Designers did not want to write netlists/schematics, and synthesis thus became the first EDA application where designs were created using an HDL. Since designers could think and write in the HDL, fewer mistakes were made. This let design complexity increase along with the silicon complexity enabled by Moore's Law.

A single designer could write many thousands of lines of HDL code and get most of it right first time. So a single designer could put together an ASIC that holds many hundreds of thousands of gates.

The Verilog PLI (Programming Language Interface) was added because it was too hard to keep up with user requests for add-on features. This made it easy for users to add C code, although there were problems with user crashes from a support point of view (most times it was not the core simulator that crashed, but user code). But it enabled new tools, libraries, and features developed by users and 3rd party companies.

Phil repeated a story that he told at the Computer History Museum. Phil was asked to give a writeup for the Sun Catalyst program and so a name for the language and the simulator had to be created. This white-board shows some of the possibilities, but it took one evening to decide that the strongest name was Verilog. The document on the right, from the Sun Catalyst program, was the first appearance of the name Verilog in print.

Simon (post-Verilog)

Verilog dominates today but in the 1980s there were many competitors: Tegas, HILO, Validsim, Speedsim, Finsim, VHDL...and more. Not to mention proprietary languages and simulators. But enhancements to Verilog and the speed of Verilog-XL slowly overcame its competition. That was the end of the netlist wars.

Peter Flake and Simon then founded Co-Design Automation with Phil Moorby as an external advisor (and eventually joined). The focus was to develop a "super" Verilog. They were influenced a bit by VHDL but felt Verilog was a better basis, and then they used syntactic similarity to C for new general-purpose programming features.

In the late 1990s there was a new set of language wars since designers needed more than Verilog for the huge chips being designed, and "everybody" had a better idea:

• VHDL (better typing, not proprietary, very widely adopted in Europe)
• Verisity (e) and Systems Science (Vera) with better verification
• SystemC and its free class library
• SpecC
• Java "there are more programmers of Java than Verilog"
• ...and Co-Design's Superlog, use Verilog but just evolve it with structure, abstraction, verification, embedded software

Gary Smith said, in 1999:

• Co-Design has a fair chance of establishing its language
• The Verilog guys are saying they have run out of steam
• The VHDL guys are pretty much saying VHDL is dead
• C++ isn't going to work at all
• C guys can't come up with a solution unless they really restrict the problem.

With the acceptance of the Co-Design donation of Superlog to Accellera in 2001, the path to SystemVerilog 3.0 was set, especially when Synopsys subsequently donated Open Vera Assertions. In 2005, it became IEEE standard 1800.

The Three of Them Today

Looking a bit older than the photograph earlier in this post!

More

Once again, the whole PDF of the HOPL paper is freely available in the ACM digital library: Verilog HDL and its ancestors and descendants.

Or you can watch the video of the DVCon session:

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