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What Is Zonal Architecture? And Why Is it Upending the Automotive Supply Chain?

Earlier this week I wrote about the electric vehicle (EV) transition, how it is happening…

Paul McLellan
• 7 min read
ota , Automotive , tier-1 , featured , zonal architecture

The Automotive Electric Vehicle Transition

The only really interesting part of the automotive industry is the electric vehicle…

Paul McLellan
• 8 min read
Automotive , Electrification , featured , ev , nev

Richard Goering, 1952-2023

I have some sad news to report. Richard Goering passed away last month at the age…

Paul McLellan
• 3 min read
featured , Richard Goering , EETimes
Breakfast Bytes

Latest blogs

GLOBALFOUNDRIES' Dual Roadmap

The Story So Far GLOBALFOUNDRIES had a 28nm Hi-K PolySi process. I think that…

• 5 min read
glofo , 22fdx , 12fdx , 14nm , emram , GlobalFoundries , 7nm , Breakfast Bytes

How to Verify MIPI Protocols

At the recent MIPI DevCon, Cadence's Ofir Michaeli gave two presentations on verification…

• 5 min read
Verification IP , layered protocol , VIP , MIPI , mipi devcon , Breakfast Bytes

What’s for Breakfast? Preview October 17th to 21st (video)

https://youtu.be/P3jRt2HEe8U Monday: GLOBALFOUNDRIES announced new nodes on their…

• less than a min read
glofo , Memory , linley processor conference , MemCon , network function virtualization , Cisco , Carnegie Mellon University , Andrzej Strojvas , VMware , Kaufman Award , 12fdx , cmu , network virtualization , pdf solutions , ST Microelectronics , GlobalFoundries , thomas skotnicki , kaufman

MemCon 2016: Storage Class Memory

MemCon, the annual all-things-memory conference originally started by Denali and…

• 7 min read
vertical flash , SCM , Memory , MemCon , LPDDR , flash , storage class memory , IBM , ddrx , DRAM , DDR , Breakfast Bytes

Cache Coherency Is the New Normal

You hear a lot about cache coherency these days. In fact, at the recent Linley processor…

• 6 min read
linley processor conference , linley group , Arteris , Linley , cache coherent , cache coherency , netspeed , cache , ARM , Breakfast Bytes

RISC-V: the Case For and Against

At the Linley Processor conference recently, there was a presentation about RISC…

• 7 min read
risc-v , linley processor conference , EEMBC , Linley , Krste Asanović , Breakfast Bytes , markus levy

DVCon Europe Preview

DVCon Europe in Munich is coming up on 19 and 20 October. For any Americans reading…

• 4 min read
Lanza , NXP , pswg , Perspec , iso26262 , DVcon , Accellera , DVCon Europe , ISO 26262 , portable stimulus , Breakfast Bytes

Cadence Implementation Flow for an ARM Cortex-A73 at 10nm

Increasingly, taking an appropriate ARM ® processor has become the standard way to…

• 4 min read
cortex-a73 , TSMC , n10 , 10nm , ARM , Breakfast Bytes

What’s for Breakfast? Preview October 10th to 14th (video)

https://youtu.be/Ej7aa83-OFM Monday: A preview of DVCon Europe on 19th/20th October…

• less than a min read
Verification IP , risc-v , Memory , linley processor conference , MemCon , flash , linley group , VIP , MIPI , EEMBC , Arteris , mipi devcon , DRAM , cache-coherency , netspeed , DVcon , DDR , DVCon Europe , sddr , ARM , verification

Verific: the Name is Short for Verification...But That's Not What They Do

I had an interesting conversation with Michiel Ligthart and Rick Carlson of Verific…

• 4 min read
SystemVerilog , parser , IEEE 1801 , Verilog , verific , UPF , VHDL , Breakfast Bytes

Tensilica Floating Point: Small, Similar Cycles and Lower Power

When I first started programming, the first programming language I learned was Fortran…

• 6 min read
lx7 , DSP , fixed point , fortran , Linley , Tensilica , mathlab , floating point

1,168 Reasons to Watch Training Bytes

Well, they told me that starting blog titles with a number is good clickbait. The…

• 2 min read
COS , self-learning , Cadence Online Support , training bytes

5nm: Do You Take the Red Pill or the Blue Pill?

I wrote recently about the TSMC OIP Symposium where they talked about future devices…

• 3 min read
tfet , 60 mV/decade , cnt , subthreshold sloope , carbon nanotube , Breakfast Bytes

How Can I Get Out of This House Without Going Anywhere Near Your Garage?

Go to any venture capitalist's website and they will have a bragging page with their…

• 2 min read
anti-portfolio , ebay , starbucks , bessemer.google , OVP , venture capital

Linley Gwennap: Specialization Spurs Processor Innovation

Every year in the fall, the Linley Group runs their processor conference. There are…

• 5 min read
security , Intel , linley processor conference , AMD , x86 , IoT , Linley , ADAS , ARM , autonomous vehicles , power , Breakfast Bytes

What’s for Breakfast? Preview October 3rd to 7th (video)

https://youtu.be/dv54rKmMLRo Monday: Options for 5nm. Silicon can only cut…

• less than a min read
60mV/decade , SystemVerilog , DSP , tensilica LX7 , CPF , Cadence videos , TSMC , parsers , Tensilica , training bytes , verific , n10 , 5nm , 10nm , ARM , floating point , VHDL , IEDM

Memories Are Made of This: Preview of MemCon

This year's MemCon is on October 11, at the Santa Clara Convention Center. Last year…

• 5 min read
vertical flash , Memory , LPDDR4 , MemCon , Micron , flash , NAND flash , Denali Party , DRAM , memcon 2016 , Breakfast Bytes

TSMC: Technology Update

Twice a year TSMC has a big meeting in San Jose. These are the times that there is…

• 7 min read
OIP , 3D packagin , HPC28 , CoWoS , IoT , 28nm , 20nm , 40ULP , fabless , TSMC , ULP , process roadmap , 55ULP , 16ff , 16nm , InFO , 16FFC , n7 , FinFET , n10 , 7nm , 10nm , foundry

System Design Enablement with Cadence and TSMC

System-on-chip (SoC) designers are always optimizing what has become known as PPA…

• 3 min read
Low Power , bvp.system-ppa , virtual platform , TSMC , Tensilica , power , Breakfast Bytes

Mellanox: Using Palladium ICA Mode

At CDNLive Israel, Yaron Netanel of Mellanox talked about his experience with Palladium…

• 3 min read
Yaron Netanel , CDNLive , debug , mellanox , Palladium , in-circuit acceleration , ICA , cdnlive israel , Breakfast Bytes

What’s for Breakfast? Preview September 26th to 30th (video)

https://youtu.be/1le_bd4o01Q Monday: System Design Enablement with Cadence and…

• less than a min read
OIP , Memory , MemCon , LPDDR , liinley , SDE , TSMC , antiportfolio , DDR , system design enablement , bessemer ventures , power , microprocessor

How to Connect Sensors with I3C

A couple of sessions at MIPI DevCon last week were on I3C. This is a new generation…

• 6 min read
MIPI , i2c , sensors , mobile , I3C

שלום from CDNLive Israel

Shalom. Today is CDNLive Israel in Tel Aviv. At least getting here from San Francisco…

• 5 min read
CDNLive , Lip-Bu Tan , cdnlive israel , perlmutter

MIPI: Not Just Mobile Any More

On September 14 and 15, MIPI held its first developer conference. For more background…

• 3 min read
5G , Automotive , 4G , CSI-2 , Standards , MIPI , mipi devcon , ADAS , I3C , Breakfast Bytes

Signal and Power Integrity Masterclass

At CDNLive Boston, I moderated a panel session on signal and power integrity with…

• 9 min read
DDR4 , CDNLive , dc-dc converters , IBM , Cisco , Oracle , cdnlive boston , advanced bus analysis , Qualcomm , compliance methodology

Are These Codecs Any Good? Netflix Tests Them

A codec compresses data for transmission. The first codec I had any close encounter…

• 5 min read
GSM , audio codec , H.265 , codec , netflix , mobile , h.264 , video codec , Breakfast Bytes

What’s for Breakfast? Preview September 19th to 23rd (video)

https://youtu.be/KKiIDaN-3CE Monday: At CDNLive Boston I moderated a panel session…

• less than a min read
cdnlive tel aviv , Paul McLellan , CDNLive , debug , mellanox , VIP , MIPI , Power Integrity , i2c , cdnlive boston , mipi devcon , Indago , Signal Integrity , cdnlive israel , I3C , what's for breakfast? , protocol verification , Breakfast Bytes , verification

Emulation Productivity: Beyond the Specs

At CDNLive in Boston, Andrew Ross of AMD presented a wealth of practical information…

• 5 min read
CDNLive , palladium z1 , Protium , Palladium , cdnlive boston , Emulation , FPGA prototyping , Breakfast Bytes
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