Custom IC, Analog, and RF Design Training Deep Dive: Part 1

We’re continuing the blog series that is taking the top 15 Online Training courses among students and professors and breaking it down into their different technical areas and sharing the supporting courses that go along with them. We started the series by deep diving into Digital Design and Signoff and we’re going to continue by exploring Custom IC, Analog, and RF Design.

Cadence custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization. In this first part, we’ll be focusing on Cadence Virtuoso tools, which work together to provide the basis of your design and all its needed testing. The tools are integrated across Cadence simulation and physical implementation tools, allowing for seamless information sharing leading to continuous verification throughout the entire analog, RF, or mixed-signal design cycle. You’ll also be introduced to Spectre and Xcelium mixed-signal options throughout the following courses.

We’re pulling the recommended training flow from the Learning Maps, which structure the Cadence Online Training courses into technical areas and difficulty levels. Some of the below courses offer a Digital Badge, once earned, you can showcase that you’re Cadence Certified on your resume, email signature, and across social channels like LinkedIn.

Summary

	1.	Virtuoso Schematic Editor*
	2.	Virtuoso Visualization and Analysis
	3.	Analog Modeling with Verilog-A*
	4.	Behavioral Modeling with Verilog AMS
	5.	Real Modeling with SystemVerilog
	6.	Real Modeling with Verilog-AMS

*One of the top courses among students and professors

Virtuoso Schematic Editor

In the Virtuoso Schematic Editor course, you learn to create and edit schematics for use with the suite of Cadence simulation and layout tools.

After completing this course, you will be able to:

• Use Virtuoso Schematic Editor L and XL to capture design schematics
• Work with Virtuoso tool assistants and corresponding workspaces to increase productivity
• Create, add, and edit:
  • Netlists and set up simulations
  • Component properties and configurations
  • Design constraints to schematics that are in the layout design
  • And more!

Virtuoso Visualization and Analysis

You’ll use the Virtuoso Visualization and Analysis tool to browse, evaluate, analyze, and plot your simulation results from Virtuoso ADE Explorer.

After completing this course, you will be able to:

• Use:
  • Virtuoso Visualization and Analysis tool to view simulation results in the waveform viewer
  • Graph tool as an integrated assistant in the Virtuoso ADE Explorer
  • Markers and cursors to precisely measure time points and signal values
  • Results Browser to select signal values in multiple result directories
  • Built-in functions available in the Direct Plot form
• Work with the available plotting and measurement options that aid in extracting information from simulated data
• Create:
  • Plotting Templates
  • Tables to display multiple results or signals that vary with simulation parameters
• And more!

Analog Modeling with Verilog-A

You’ll learn about Virtuoso ADE Explorer and Spectre Circuit Simulator to simulate analog circuits with Verilog-A models. Verilog-A is a high-level language that uses modules to describe the structure and behavior of analog systems and their components. You use the Verilog-A syntax, structure Verilog-A modules, and generate symbols for your Verilog-A cells for use in a system hierarchy. You also learn to format output data and to use waveform filters to improve simulation performance. Finally, you examine the AHDL Linter feature to detect potential bugs in the Verilog-A codes.

After completing this course, you will be able to:

• Determine the importance of the top-down design methodology for accelerating complex system development
• Write behavioral models of electrical circuits
• Create, edit, and simulate a variety of analog models written in the Verilog-A language using the Virtuoso ADE Explorer and the command-line environment
• Verify that Verilog-A modules properly describe the intended function
• Use software design tools to facilitate model development
• And more!

Behavioral Modeling with Verilog-AMS

In this advanced Engineer Explorer course, you explore an in-depth approach to behavioral modeling of analog and mixed-signal design blocks and systems. You’ll examine digital, analog, and mixed-signal modeling concepts.

After completing this course, you will be able to:

• Apply the concepts of behavioral modeling and know when to employ models to your advantage
• Create Verilog, Verilog-A, and Verilog-AMS behavioral models to perform given functions
• Verify the functionality and performance of the models that you create
• Generate a library of common functions
• Explore some of the best practices for modeling analog components
• And more!

Real Modeling with SystemVerilog

In this advanced Engineer Explorer course, you focus on Real-Number Modeling (RNM) using the SystemVerilog language, in a mixed approach borrowing concepts from the digital and analog domains to enable high-performance digital-centric, mixed-signal verification. In this course, you learn how to model analog block operation as discrete real data to dramatically improve top-level verification performance using SV real data type and nettypes. It stresses on SystemVerilog 2012 Extended Nettype Capabilities (built-in, UDT/UDR) and Interconnects. Most of the labs in this course are in command-line mode using the Xcelium simulator with the mixed-signal option.

After completing this course, you will be able to

• Identify how Real-Number Modeling (RNM) using SystemVerilog enables high-performance digital-centric, mixed-signal SoC verification
• Create real-number models with SystemVerilog real variables and nettypes
• Apply the real modeling techniques for creating analog operations and functions
• Identify SystemVerilog 2012 Extended Nettype Capabilities (built-in, UDT/UDR) and Interconnects
• And more!

Real Modeling with Verilog-AMS

In this advanced Engineer Explorer course, you learn how real number modeling using Verilog-AMS (wreal) enables high-performance digital-centric, mixed-signal verification how to model analog block operation as discrete real data for such. You must have a working knowledge of the Virtuoso AMS Designer simulator or you must take the Virtuoso AMS Designer course.

After completing this course, you will be able to:

• Identify and create real number modeling using Verilog-AMS (wreal)
• Verify the functionality and performance of the wreal models
• Use the advanced wreal modeling features
• Review some of the tips and tricks that you can apply while creating and simulating wreal models
• And more!

After completing these courses, you’ll have a better grasp on the functionality of Virtuoso, providing the basis of your design and the necessary testing along the way; You’re introduced to Spectre Simulation, which contains multiple solvers to allow a designer to move easily and seamlessly between circuit-, block-, and system-level simulation tasks;  And, you learn about Xcelium simulation that supports both single-core and multi-core use models.

This is just the beginning of the Custom IC, Analog, and RF design training deep dive, so stay tuned for the blogs to come that’ll explore more courses that’ll increase your knowledge of Cadence tools.

How to enroll in Online Training:

All Online Training courses are available for self-enrollment on the Cadence Learning and Support system, located under the “Learning” tab.

To get a Learning and Support account:

• Cadence University Program and CMC Microsystems, please reach out to universityprogram@cadence.com
• Europractice, please reach out to MicroelectronicsCentre@stfc.ac.uk