Digital Design and Signoff Training Deep Dive: Part 2 – Implementation

Welcome back to our series, and if you’re new here, thanks for joining us today! We’re going to be looking at another part of Digital Design and Signoff solutions: Implementation. We’ll be building off the recommended courses from our first Deep Dive into Digital Design and Signoff blog as we continue to support you on your journey to becoming a Design pro, by sharing the Cadence Online Training courses you should take to learn these tools.

So, we know that designs are getting bigger and more complex, this translates to more challenging power, performance, and area (PPA) targets. To help with the complexity, we’re going to be breaking down the courses you should take to learn about the Cadence Innovus Implementation System, which is optimized for the most challenging designs, helping you get an earlier design start with a faster ramp-up. With unique new capabilities in placement, optimization, routing, and clocking, the Innovus system features an architecture that accounts for upstream and downstream steps and effects in the design flow.

We’re pulling the recommended training flow from the Learning Maps, which structure the iLS Online Training courses into technical areas and difficulty levels. Some of the below courses offer a Digital Badge, once earned, you can showcase that you’re Cadence Certified on your resume, email signature, and across social channels like LinkedIn. If you’ve completed the courses from Part 1, you can go ahead and start learning, but if not, it’ll help to take Basic Static Timing Analysis and Fundamentals of IEEE1801 Low Power Specification in addition to the below courses.

Summary:

	1.	Innovus Implementation System (Block)*
	2.	Innovus Implementation System (Hierarchical)
	3.	Low-Power Flow with Innovus Implementation System
	4.	Innovus Clock Concurrent Optimization Technology for Clock Tree Synthesis

*One of the top courses among students and professors

Innovus Implementation System (Block)

In this course, you learn how to use the Innovus Implementation System software to achieve the best power, performance and area (PPA) for your design. You learn several techniques for floorplanning and placement using the GigaPlace solver-based. You will learn how to set up and run the concurrent clock and datapath optimization engine to enhance cross-corner variability and boost performance with reduced power.

After completing this course, you will be able to:

• Import and floorplan a design
• Run:
  • Placement and optimization using GigaPlace technology
  • Timing analysis and debug results
  • Optimization for power, performance and area
  • The slack-driven router with track-aware timing optimization
  • Global and detail routing for timing and signal integrity
  • ECOs on a design
  • Design verification for geometry, connectivity, antenna and metal fill
  • Database access commands
  • Foundation Flow scripts
• Learn more!

Innovus Implementation System (Hierarchical)

In this course, you explore the features of the Innovus Implementation System for creating and implementing a hierarchical design. You learn several techniques to floorplan your design, create partitions, run place and route, and optimize the design to close timing. You learn techniques to reduce the memory size and run time by using interface logic models (ILMs).

After completing this course, you will be able to:

• Floorplan and create partitions for your design
• Implement the blocks and the top-level design using various methods after analyzing the benefits and drawbacks of each method
• Generate and run customized scripts (Foundation Flow Scripts) that contain the recommended commands and options to implement your design
• Learn more!

Low-Power Flow with Innovus Implementation System

In this course, you explore and implement several low-power techniques to reduce both dynamic and leakage power during synthesis and design implementation.

After completing this course, you will be able to:

• Implement:
  • Multi-Supply Multi-Voltage (MSMV) regions to reduce power consumption
  • Low-power clock tree
  • MSMV-aware detail routing
• Run concurrent timing, MSV optimization, and multi-VT (leakage) optimization
• Analyze data and debug power problems at different stages of the flow
• Learn more!

Innovus Clock Concurrent Optimization Technology for Clock Tree Synthesis

In this course, you learn how to use the Clock Concurrent Optimization (CCOpt) technology, which is integrated into Innovus Implementation System software to achieve the best clock tree for your power, performance and area (PPA) targets for your design. You learn clock tree theory and concepts as well as practical guides on how to set up properties and techniques to implement and debug the generated tree with the Clock Tree Debugger (CTD) tool.

Learning Objectives

After completing this course, you will be able to:

• Identify where in the digital implementation flow clock tree synthesis is run
• Evaluate:
  • Benefits and challenges of useful skew vs. a skew balanced clock
  • Advantages and disadvantages of various clock structures
• Implement:
  • Clock tree using CCOpt technology using the generated constraints
  • Flexible H-tree
• Learn more!

After completing these courses, you’ll be one step closer to becoming a Design pro. Continue to follow along with the blog series to learn which courses are recommended for mastering Digital Design and Signoff.

How to enroll in Online Training:

All Online Training courses are available for self-enrollment on the Cadence Learning and Support system, located under the “Learning” tab.

To get a Learning and Support account:

• Cadence University Program and CMC Microsystems, please reach out to universityprogram@cadence.com
• Europractice, please reach out to MicroelectronicsCentre@stfc.ac.uk

Wrap-up

Part 1 covers Synthesis and Test, if you already have experience in that area, then you can jump right into Part 2: Implementation. If starting here, you should add Basic Static Timing Analysis and Fundamentals of IEEE1801 Low Power Specification into your learning plan in the below order: 

	1.	Basic Static Timing Analysis*
	2.	Innovus Implementation System (Block)*
	3.	Innovus Implementation System (Hierarchical)
	4.	Fundamentals of IEEE1801 Low Power Specification
	5.	Low-Power Flow with Innovus Implementation System
	6.	Innovus Clock Concurrent Optimization Technology for Clock Tree Synthesis

*One of the top courses among students and professors