Cadence Academic Network Blogs

As we continue this blog series, we’re going to keep looking at System Design and Verification Online Training courses. In Part 1, we went over Verilog language and application, Xcelium simulator, and introduced SystemVerilog. We’ll now dive a little deeper into SystemVerilog and introduce JasperGold.

Cadence’s system design and verification solutions, which provide simulation, acceleration, emulation, and management capabilities, accelerate development time and reduce integration time by up to 50%. Using SystemVerilog constructs, the design and verification can be even more efficient and effective. We’ll also introduce, Specman, which will explain how to create an e language reusable block-level verification environment, and JasperGold, which takes a completely different paradigm to older and more widely adopted methods of verification and simulation by using Formal Analysis.

Taking these courses will improve your understanding of how to incorporate Cadence tools in order to improve your designs and verification.

Summary

	1.	SystemVerilog Accelerated Verification with UVM*
	2.	SystemVerilog Assertions
	3.	Specman Fundamentals for Block-Level Environment Developers
	4.	SVA, Formal and JasperGold Fundamentals for Designers
	5.	JasperGold Formal Expert

*One of the top courses among students and professors

SystemVerilog Accelerated Verification with UVM

Universal Verification Methodology (UVM) is the IEEE1800.1 class-based verification library and reuse methodology for SystemVerilog. The UVM class library provides the basic building blocks for creating verification data and components. The UVM methodology enables engineers to quickly develop powerful, reusable, and scalable object-oriented verification environments.

This course teaches you UVM in exactly the same way as you would use the methodology in a real-life project. The goal is to allow you to walk away from this course and immediately be effective in working on UVM projects.

After completing this course, you will be able to:

• Understand the features and capabilities of the UVM class library for SystemVerilog
• Create and configure reusable, scalable, and robust UVM Verification Components (UVCs)
• And more!

SystemVerilog Assertions

This course gives you an in-depth introduction to SystemVerilog Assertions (SVA), together with guidelines and methodologies to help you create, manage, and debug effective assertions for complex design properties. The course is packed with examples, case studies, and hands-on lab exercises to demonstrate real-life applications of SVA.

After completing this course, you will be able to:

• Explain
  • Advantages of assertion-based verification (ABV) using SystemVerilog Assertions
  • Issues regarding verification completeness
  • Formal Analysis, what it does, how it works and run basic proofs
• Describe
  • Structure of SVA
  • Scalable methodology for reuse of SVA properties
  • Common behaviors that SVA cannot describe and how to overcome these issues
• And more!

Specman Fundamentals for Block-Level Environment Developers

In this course, you create an e language reusable block-level verification environment and simulate it with the Xcelium simulator and analyze the simulation with the SimVision graphical simulation analysis environment.

The course provides an introduction to the e language in the context of the Coverage-Driven Verification (CDV) methodology. You use the standard Universal Verification Methodology (UVM-e) to build a reusable verification environment.

After completing this course, you will be able to:

• Explain the need for and nature of the coverage-driven verification methodology
• Implement basic e syntax
• Develop
  • Interface UVC for the Simple Packet Protocol
  • Sequence library for stimulus generation
  • Module UVC for the SPP router module
• Implement a mechanism to handle reset during verification and cleanly terminate the simulation
• And more!

SVA, Formal and JasperGold Fundamentals for Designers

This course introduces SystemVerilog Assertions (SVA) in a very pragmatic way, including how to code SVA properties which are efficient for Formal Analysis. Formal Analysis is a completely different paradigm from the older and more widely adopted methods of verification like simulation. As such, the fundamental objectives, capabilities, limitations, setup and initialization requirements, in addition to analysis and interpretation of results, need to be well understood before we can make effective use of FA tools and specialized JasperGold Apps.

After completing this course, you will be able to:

• Define reusable, functionally correct SVA properties which are efficient for Formal tools
• Set up, run and analyze results from Formal Analysis
• Identify designs upon which formal is likely to be successful
• Set up and run the JasperGold Apps named Superlint and X-Propagation
• And more!

JasperGold Formal Expert

This course is intended for users of JasperGold wishing to improve Formal Verification Performance by using advanced techniques. There is a 50/50 split between lectures and hands-on labs which allows the user to gain experience of the advanced techniques discussed in the course.

After attending the course, you will be able to:

• Write
  • Simple and efficient assertions with a small complexity footprint
  • Effective deadlock assertions with both safety and liveness semantics
• Apply
  • Abstraction and reduction techniques to deal with the complexities of a formal testbench
  • Checker abstraction techniques to deliver an efficient Formal Scoreboard
• And more!

How to Enroll in Online Training:

All Online Training courses are available for self-enrollment on the Cadence Learning and Support system, located under the “Learning” tab.

To get a Learning and Support account:

• Cadence University Program and CMC Microsystems, please reach out to universityprogram@cadence.com
• Europractice, please reach out to MicroelectronicsCentre@stfc.ac.uk

These courses will teach you more advanced use of SystemVerilog and introduce you to Specman, and JasperGold and the different ways it can optimize Formal Analysis. Keep following along with this blog series as we conclude it with a post about C++ and SystemC languages. All courses will improve your understanding of System Design and Verification.