Cadence Academic Network Blogs

We’re concluding the Online Training Deep Dive blog series, which has been taking the top 15 Online Training courses among students and professors and breaking them down into their different technical areas and sharing the supporting courses that go along with them.  The first part explored Digital Design and Signoff, then we went into Custom IC, Analog and RF design, and finally, we’ll be taking a closer look into the System Design and Verification courses.

Cadence system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities, which enables you to reduce system integration time by up to 50%, accelerate IP development, early software development, SoC integration, concurrent hardware/software development, and integrate system validation. The courses we introduce will introduce you to these solutions and teach you how to apply them.

So, let’s jump in!

Summary

	1.	Verilog Language and Application
	2.	Xcelium Simulator
	3.	Foundations of Metric-Driven Verification
	4.	XCelium Integrated Coverage
	5.	Metric-Driven Verification Using vManager
	6.	SystemVerilog for Design and Verification*

*One of the top courses among students and professors

Verilog Language and Application

The Verilog Language and Application course offers a comprehensive exploration of the Verilog HDL and its application to ASIC and programmable logic design. This training course covers all aspects of the language, from basic concepts and syntax through synthesis coding styles and guidelines to advanced language constructs and design verification.

After completing this course, you will be able to:

• Use fundamental Verilog constructs to create simple designs
• Ensure that Verilog designs meet the requirements for synthesis
• Develop Verilog test environments of significant capability and complexity
• Learn more

Xcelium Simulator

In this course, you are introduced to the new Cadence 3rd generation Xcelium simulator. All concepts are explained with the help of hands-on labs.

After completing this course, you will be able to:

• Perform simulation using the Cadence Xcelium simulator tool for design verification and debugging
• Use the different commands of Xcelium simulator
• And more!

Foundations of Metric Driven Verification

Metric Driven Verification or MDV is a powerful layer of methodology that sits above the Verification Testbench Environment. It provides guidelines and tools for using/analyzing metrics and automation to maximize the benefits of the verification testbench. It is a data-driven decision-based flow that improves the predictability, productivity, and quality of the verification effort.

After completing this course, you will be able to:

• Recognize current industry verification challenges
• Explore Metric Driven Verification
• Understand:
  • Different phases of the MDV Methodology Cycle
  • Plan based MDV
  • Testcase driven MDV
• Perform
  • Plan and metrics analysis
  • Regression results management
• And more!

Xcelium Integrated Coverage

This course explores Xcelium integrated coverage features. The course addresses coverage of VHDL, Verilog and mixed-language designs. The course discusses the collection and analysis of the following types of coverage:

• Code (branch, expression, toggle, state, and arc) coverage
• Data-oriented functional coverage using SystemVerilog cover groups
• Control-oriented functional coverage using SystemVerilog assertions and the PSL

After completing this course, you will be able to:

• Effectively use the Xcelium integrated coverage with your VHDL, Verilog, and mixed-language designs
• Learn more

Metric Driven Verification Using Cadence vManager

Cadence vManager is a revolutionary tool which is completely based on the Metric Driven Verification methodology. It is a complete database-driven architecture of Incisive Enterprise Manager with powerful new features for tracking verification progress.

After completing this course, you will be able to:

• Define and review the Cadence Metric Driven Verification (MDV) methodology
• Use the MDV in a verification project
• Recognize the importance of verification planning and develop a vPlan
• Set up the server profile for the vManager server
• Create a regression run with a Verification Session Input File (VSIF)
• And more!

SystemVerilog for Design and Verification

This course gives you an in-depth introduction to the main SystemVerilog enhancements to the Verilog hardware description language (HDL), discusses the benefits of the new features, and demonstrates how design and verification can be more efficient and effective when using SystemVerilog constructs.

After completing this course, you will be able to:

• Understand and use the SystemVerilog RTL design and synthesis features
• Appreciate and apply the SystemVerilog verification features
• And more!

 How to enroll in Online Training:

All Online Training courses are available for self-enrollment on the Cadence Learning and Support system, located under the “Learning” tab.

To get a Learning and Support account:

• Cadence University Program and CMC Microsystems, please reach out to universityprogram@cadence.com
• Europractice, please reach out to MicroelectronicsCentre@stfc.ac.uk

After completing these courses, you’ll be on your way to being well versed in System Design and Verification. In the next part, we’ll go over some more advanced SystemVerilog courses and introduce JasperGold formal verification suite. Stay tuned!