Virtuosity: Introducing Automated Device Placement and Routing in Virtuoso

The semiconductor industry has long relied on electronic design automation (EDA) software for IC design. As the industry evolved over the years, so did the EDA tools.

However, the evolution of EDA tools in the analog and full custom space wasn’t quite as dramatic as that on the digital side. There were several reasons behind this, the most important being the difficulty in producing layouts through automation that match the quality of those crafted by hand. In addition, analog designs were often based on older process nodes as they lacked the compelling motivations (power, performance, area, and cost) of digital designs to move to the newer nodes.

The phenomenal growth of analog and mixed-signal (A/MS) system on chips (SoCs) in recent years, fueled by drivers such as mobile technology and IoTs, were the game changers. Analog and mixed-signal circuits could no longer be designed at the same pace. The complexity of the newer nodes forced such designs to follow a structured layout methodology, similar to their digital counterparts, along with an increasing need for automation. However, the inherent analog layout requirements of grouping and matching still remained, making it a unique challenge.

As the undisputed industry leader in analog and full custom design solutions, the inevitable question for Virtuoso^® technology was not "if" but "when" it would provide such an automated functionality to the end users.

The time is now!

ICADVM18.1 just got a lot more compelling with the launch of a Fully Automated Device-Level Placement and Routing Solution that is geared towards advanced nodes and has been developed in partnership with industry leaders for representative foundries. This solution takes users through an assistant-driven flow that automates every step along the way, from constraint creation and grid generation to placement, fill insertion, and routing—producing a layout in minutes with nothing but a schematic as the input. The solution can thus be used to quickly generate multiple layouts for extraction and re-simulation, providing circuit designers with valuable feedback early on and eliminating costly iterations. Additionally, it can provide layout designers with a solid starting point that can be refined incrementally and finished very quickly.

What's Next?

In the upcoming posts in this series, we will cover each step of this flow:

Automated device grouping and constraint creation
Automated grid generation for placement and routing
Automated device placement with different aspect ratios
Automated base layer fill insertion
Automated tree-style device routing

We look forward to taking you through this exciting journey into the world of analog layout automation. Watch out for our posts every alternate week!

Related Resources

Rapid Adoption Kits:

Flow Guide:

Virtuoso Automated Device-Level Layout Flow Guide

For more information on Cadence circuit design products and services, visit www.cadence.com.

About Virtuosity

Virtuosity has been our most viewed and admired blog series for a long time that has brought to fore some lesser known, yet very useful software and documentation improvements, and also shed light on some exciting new offerings in Virtuoso. We are now expanding the scope of this series by broadcasting the voice of different bloggers and experts, who would continue to preserve the legacy of Virtuosity, and try to give new dimensions to it by covering topics across the length and breadth of Virtuoso, and a lot more… Click Subscribe to visit the Subscription box at the top of the page in which you can submit your email address to receive notifications about our latest Virtuosity posts.

Happy Reading!

- Sravasti Nair

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