Start Your Engines: Best Practices for Converting a Logic Signal to Electrical Value with Mixed-Signal Modelling

Cadence Spectre AMS Designer is a high-performance mixed-signal simulation system. The ability to use multiple engines and drive from a variety of platforms enables you to "rev up" your mixed-signal design verification and take the checkered flag in the race to the market. The Start Your Engines! blog series will provide you with tips and insights to help you tune your simulation performance and accelerate down the road to productivity.

Bonjour!

In this post, I will explain how you can easily convert a logic signal to an electrical value using the Verilog-AMS standard language defined by Accellera.

First, let me draw the symbol for this model.

The model is named L2Econv, and it has:

• One logic input port named l
• One electrical output port, named e 

The following table describes the model parameters:

The L2Econv module can be considered equivalent to a level shifter. The only difference is that instead of an electrical input, it has a logic input. The output is electrical and operates with the supply value.

The disciplines.vams file is included in this model to provide the necessary Verilog-AMS discipline definitions (electrical) and the definition of the voltage and current access functions.

L2Econv Model

The idea behind this model is to:

• Declare the mandatory parameters to define the conversion of logic values to analog.
• Detect the input logic event and define the corresponding analog value levels through the estate.
• Trigger the event solver and analog synchronization every time the state of the estate variable changes. This is done automatically with the Verilog-AMS transition filter. The transition filter will introduce a delay if the parameter td is greater than zero.

The behavioral code is as follows:

It lets you perform a logic-to-electrical conversion. Inside the analog block, you generate the current branch to define a Norton generator, where rout is the value of the output resistor.

This model is very compact. With one initial, two always, and one analog block, this behavioral model is created.

Now, you just need to test the model.

The testbench is a stimuli digital generator source driving the logic L2Econv module input. It sends the logic values 1’b0, 1’b1, 1’bx, 1’bz sequentially.

With SimVision MS Debug, you can automatically create the schematic. It also annotates values in the schematic, as shown in the figure. The L2Econv module described in Verilog-AMS is a mixed-signal model, so the instance is highlighted in blue. The figure shows the stimuli digital generator driven by 1’b1. The L2Econv module then translates this value to 1 volt.

The plotted waveforms are as shown in the following figure:

v

In this figure:

• The waveform in green displays the logic input, which is a logic voltage. It is easy to see the signal transmission to 1’b1 and X and Z states.
• The waveform in yellow displays the electrical output, with conversion operation to electrical values. In our code, logic X and Z states are converted to zero volt.

The following waveform shows the transition operation:

In this waveform:

• The logic transition is converted in the electrical domain with a delay of td=100 pico seconds.
• There is a transition time value of tt=10 pico seconds to pass from 0 volt to 1 volt.

Interactive Debugging with SimVision MS Debug

You can send an L2Econv instance to the Source Browser, perform a step-by-step operation investigation, or set a breakpoint at a specific line, as shown in the figure. The breakpoint causes the debugger to pause the simulation when it reaches the line execution. This allows us to examine the input and output, the internal register, and variable values. When you launch a batch simulation, you cannot execute inteactive debug and understand the model line by line and step by step operation, study the source code operation in detail. SimVision MS Debug provides you visibility on the code operation. The invisible value changes in the internal analog and digital variables become visible.

SimVision MS Debug lets you annotate internal variables and display their values at the current time. These values that are usually invisible during a batch simulation become visible.

In the figure shown below, we observe that the simulation is paused because a breakpoint is set up at line number 21.

Common Errors

• Forgetting to use the transition filter. The Verilog-AMS transition filter has the advantage of taking care of the event solver and analog solver synchronization automatically.
• Creating a voltage branch instead of the current branch in the Verilog-AMS behavioral model. Here we created a current branch. This is a Norton generator with rout. Because the analog solver is based on the modified nodal analysis, current branches are translated to direct alteration of nodal equations. Instead, a voltage branch usage will increase the number of equations to be resolved, and the test bench analog solver could become slower.

Conclusion

• In general, a mixed-signal engineer should always use the Verilog-AMS transition filter when they need to convert a digital discrete variable to electrical.
• The transition filter smooths out piecewise constant waveforms.
• The transition filter imitates transitions and delays on digital signals for non-piecewise constant signals.
• In addition, this transition function can provide controlled transitions between discrete signal levels by setting the rise time and fall time of signal transitions. Here, we decided to define only the rise time argument in the transition function because the fall time automatically reuses the value of the rise time.
• The behavioral logic-to-electrical concepts presented here can be reused for connecting module creation with the Cadence Verilog-AMS or SystemVerilog-AMS compilers delivered inside Xcelium. This is very easy. You just need to replace the word module with the connectmodule in the behavioral codes and create a .vams file for the connect rules.
• SimVision MS Debug is very valuable for interactive debugging of such mixed-signal models, with Source Debugger, Design Browser, Waveform window, and Schematic Tracer.

I hope you are now excited to try this model and SimVision MS Debug features out for yourself! If you need more details, contact Cadence Customer Support team.

~ Andre Baguenier

Related Resources

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About Start Your Engines

The Start Your Engines series brings you blog posts from several analog/mixed-signal subject matter experts on a variety of topics, such as introduction to the new features in AMS Designer, tips for enhanced working with existing features, and much more. To receive notifications about new blogs in this series, click Subscribe and submit your email ID in the Subscriptions box.