Virtuoso Meets Maxwell: Creating Connectivity Between Die and BGA Package for IC Packaging Process

'Virtuoso Meets Maxwell' is a blog series aimed at exploring the capabilities and potential of Virtuoso RF Solution and Virtuoso MultiTech. So, how does Virtuoso meets Maxwell? Now, the Virtuoso platform supports RF designs, and the RF designers measure the physical and radiation effects by using the Maxwell's equations. In addition to providing insights into the useful software enhancements, this series broadcasts the voices of different bloggers and experts about their knowledge and experience of various tools in the Virtuoso IC-Packaging world along with the nuances of RF, microwave, and high frequency designs. Watch out for our posts on Mondays.

Before the creation of die and package layout can begin, logical connectivity between these two fabrics need to be established. Based on the number of input or output and power or ground connections needed, the physical size and pin arrangement of the IC and package can start.

Establishing and managing logical connectivity between the die and package is a critical step in an IC packaging process. This effort involves many teams collaborating together to optimize the signal and power delivery interconnect scheme that will satisfy electrical, thermal, and signal integrity requirements as well as reduce manufacturing costs and improve reliability by reducing unnecessary metal layers and vias by keeping routes as short as possible.

A challenge that needs to be addressed at the early stages of I/O planning is power delivery planning. Power planning is a step that typically is done during floorplanning in which a power grid network is created to distribute power to each part of a die and package equally.

Another challenge is to optimize critical signal bump and ball locations that mitigates crosstalk and coupling issues between a die and package. One common strategy is to keep the input signals away from the output signals as much as possible. Often, a before and after route signal integrity/power integrity analysis is required to identify potential issues before the final pinout is finalized.

To manage the physical locations of the die bumps and/or package balls, usually a ball/bump map is created. This process is called Bump-Ball I/O planning.

Bump/Ball mapping helps the engineer or system architect achieve the right balance of the cross-substrate interconnect integration for optimal electrical, thermal, and physical performance with cost and manufacturing ability in mind.

Typically, a package ball map or a die bump map is created in Microsoft Excel, which is used to define where the connections will be optimized between an IC and a BGA package. Many semiconductor manufacturers use Microsoft Excel spreadsheet as a general-purpose tool for defining the ball matrix on BGA packages. The reason being that Microsoft Excel is universally available and understood, therefore, data about the ball assignment versus signal is often transmitted in this fashion. Each cell contains a pin number and a net name. Color coding is very useful in visualizing where the power, ground, and interface signals are physically located.

Example Bump Map

Example Ball Map

Once the I/O’s have been optimized and distributed (assigned) and the bump/ball map is completed, the nets are assigned to the die bumps in Virtuoso layout and an area-IO (or bondfile) text file is exported to the package design team. A simple script converts the area-IO/bondfile format into a die text-in format that Allegro Package Designer SiP Layout Option can import. After the die text file is imported into SiP Layout Option, the die footprint is now instantiated into the BGA package layout.

                                Die footprint (Flip chip)

Assuming that the BGA package is already instantiated in the layout, connectivity between the die and the BGA package are now displayed as rats nets (aka flight lines) and the physical layout process can begin.   

                  Die (Flip chip) logically connected to the BGA package

You can create a BGA package using the BGA Text-In method if one doesn’t already exist.

Creating a BGA Package

If a BGA footprint already exists in the your library, it is imported into SiP Layout Option. However, if the target BGA does not already exist in the library, the following methods are available for creating BGA footprints using SiP Layout Option:

• BGA Text-In
• BGA Generator

Depending on what information is available to start with will determine which method to use. For example, you may consider using the BGA Text-in method when there is an existing file that contains delimited information, such as the BGA pin numbers, pin X and Y locations, and net names. The BGA Text-In utility can then be used to parse this information into a format that can easily be used by SiP Layout Option to create the BGA footprint.

If you want to perform an early “what-if” or feasibility study to determine the size of a BGA, you can use the BGA Generator. The BGA Generator prompts for key BGA parameters, such as BGA dimensions, pin arrangement, pin spacing, number of pins, pin numbering, and padstack name.

By using either of the above-mentioned methods, a BGA footprint is created in less than a minute.

                               BGA footprint

Now that the die and BGA devices are instantiated into the layout and the connectivity between these devices have already been established, the layout designer can now begin the physical layout process.

Using auto and auto-interactive routing functionality within Allegro Package Designer SiP Layout Option, the layout designer can quickly route the design while adhering to the manufacturing design rules:

                            Die (Flip chip) physically routed on the BGA package

                
Michael Goode

Related Resources

• Virtuoso RF Solution
• Virtuoso MultiTech Framework Guide
• Virtuoso RF Solution Guide
• Virtuoso Electromagnetic Solver User Guide
• What’s New in Virtuoso

For more information on Cadence circuit design products and services, visit www.cadence.com.

Related Free Trials

• Virtuoso RF Solution - Module Layout with Edit-in-Concert Rapid Adoption Kit
• Virtuoso RF Solution - EM Analysis Rapid Adoption Kit

About Virtuoso Meets Maxwell

Virtuoso Meets Maxwell series includes posts about the next-generation die, package, and board design flow with a focus on reinventing and optimizing the design process to ensure that the designer remains a designer! Keep watching!

Click Subscribe to submit your email address for receiving notifications about our latest Virtuoso Meets Maxwell posts.