Virtuosity: Custom IC Design Flow/Methodology – Schematic Capture and Circuit Simulation

The current challenge in custom/mixed-signal design is to have a fast and silicon-accurate methodology. In this blog series, we are exploring the Custom IC Design Flow and Methodology stages. This methodology directly addresses the primary challenge of predictability in creating these IC designs by maximizing speed and silicon accuracy throughout the design process. The methodology also covers the key design domains of analog, custom digital, and RF, and supports their integration with digital standard cell blocks. 

Design Flow Stages

The following figure illustrates the five key design stages in the Custom IC design methodology and the tools used at each stage. In this blog, we will explain the Schematic Capture and Circuit simulation stage.

Circuit Schematic Capture

Schematic Capture and Circuit Simulation is the first stage of circuit design. At this stage, we run pre-layout circuit simulations. The ADE Explorer/ADE Assembler schematic testbench is set up as for the Sample and Hold (S/H) ADC design below and mixed-signal simulation is performed to analyze the basic operation of the analog blocks with the initial HDL-level blocks. Detailed circuit design and analysis is then performed to verify the basic functionality of the block at the transistor level. This uses the testbench developed for the HDL simulations to analyze the performance specifications of the analog block.

Simulation Results - ViVA XL Waveforms

The ViVA XL Analysis window shows the comparison of the transistor-level schematic waveform against the HDL simulation. For the Sample and Hold (S/H) ADC design in discussion here, the ViVA XL Analysis waveform infers that the S/H output waveform from the HDL-based simulation and the transistor-level simulation are very close.

ADE Assembler Results Display

After performing the ViVA XL Analysis simulation, a simulation run is performed over the Process Voltage Temperature (PVT) variation corners and the worst-case corner is identified. For this testbench set up, the worst-case corner is the Slow-Fast (SF) corner. Talking about the measurement expression for the current testbench set up, the Acquisition time, Tacq, determined from the simulation is 5.566ns, which is also highlighted in the Results tab of the ADE Assembler maestro testbench below. The specification criteria to be met is <4ns for this expression.

Circuit Optimization in ADE

This worst-case corner is then optimized using the Local Optimization technique to bring all the performance parameters within their specified limits, as shown below. You can see that the optimized value for the acquisition parameter, Tacq, is now 3.352ns for even the worst-case corner.

After the worst-corner optimization is achieved, a final corner analysis is performed. The final corner analysis uses the optimized Design Variable values obtained from the previous step to check and finalize the component values that will be used in the next design cycle to ensure the performance parameters are within their specified limits.

To try out the Custom IC Design flow, you can download a series of RAKs from the Cadence Learning and Support website. In this RAK series, each stage in the Custom IC Design Flow and Methodology is explained in detail, supported by a downloadable test database to help you try out the steps. The RAK series begins at the introduction of the design flow, followed by the schematic and layout design of the Sample and Hold ADC block, which is then followed by a pre-layout simulation setup and run. Then the RAK covers extraction of the individual blocks inside the top-level Flash ADC design, followed by a final post-layout simulation analysis to ensure the pre- and post-layout results are consistent and the specifications are met. The GDSII (Graphic Database System II) file is created as a final step, which can then be sent to the foundry for fabrication/manufacturing of the chip. You can run each stage in the RAK independently, or work your way through the entire flow.

To read more about the next design stage -Circuit Layout Design - in the Custom IC Design flow, stay tuned for our next blog in the series.

For more information on Cadence Custom IC circuit design products and services, visit www.cadence.com.

Related Resources

Rapid Adoption Kit	Custom IC Design Flow/Methodology  Custom IC Design Flow/Methodology: Schematic Capture & Circuit Simulation
User Guides​	Virtuoso Schematic Editor User Guide Virtuoso ADE Explorer User Guide Virtuoso ADE Assembler User Guide Spectre Classic Simulator, Spectre APS, Spectre X, and Spectre XPS User Guide Spectre AMS Designer and Xcelium Simulator Mixed-Signal User Guide
Application Notes	Circuit Optimization
Blogs	Virtuosity: Custom IC Design Flow/Methodology – Introduction

Contact Us

For any questions or general feedback, please write to custom_ic_blogs@cadence.com.

Happy reading, and stay safe!

Ashish Patni, Harsh Gupta

About Virtuosity

Virtuosity has been our most viewed and admired blog series for a long time. The series has brought to the fore some less well-known yet very useful software and documentation improvements and has also shed light on some exciting new offerings in Virtuoso. This series broadcasts the voices of different bloggers and experts, who continue to preserve the legacy of Virtuosity and try to give new dimensions to it by covering topics across the length and breadth of the Virtuoso environment, and a lot more.