Virtuoso Meets Maxwell: Custom Passive Device Authoring - Part 1 (Automatic Marker Shape Generation)

'Virtuoso Meets Maxwell' is a blog series aimed at exploring the capabilities and potential of Virtuoso® Multi-Technology Solution, Virtuoso Electromagnetic Simulations, and Virtuoso RF Solution. So, how does Virtuoso meet Maxwell? Now, Virtuoso platform supports RF designs, and the RF designers measure the physical and radiation effects by using Maxwell's equations. In addition to providing insights into the useful software enhancements, this series broadcasts the voices of different bloggers and experts about their knowledge and experience of various tools in the Virtuoso IC-Packaging world, along with the nuances of RF, microwave, and high-frequency designs. Watch out for our posts on Mondays.

You probably heard about the release of Cadence EMX Designer. This blazing fast layout synthesis tool offers significant productivity gains and creates a lot of interest and excitement at trade shows and conferences like International Microwave Symposium (IMS).

The performance of RF circuits heavily depends on the characteristics of passive devices, such as inductors or transformers. To meet the specification of their products, RF designers cannot always rely on the foundry-provided PDK devices. Indeed, considerable time and effort is spent to create optimized custom passive devices. EMX Designer plays an important role in reducing the time and effort for optimizing the devices.

Another requirement is the integration of newly designed custom passive devices into the overall development cycle. The challenge that RF designers face is that all design, simulation, and physical verification flows must support these new non-PDK devices.

When you think for a moment about the different parts of a PDK, you will quickly realize that the device-specific information is stored at many locations. Starting from the device layout, you need a symbol view for schematic generation, a device model for circuit simulation, Component Description Format (CDF) setup, and stopping views for multiple netlisters, and more. For physical signoff verification, marker shapes are required for device-specific DRC rules or to exclude the devices from metal fill. And eventually, the new devices must be extracted during the Layout Versus Schematic (LVS) check. Until today, RF designers spend a prohibitively large amount of time to create this data. They even accept verification gaps when part of this data is missing.

The new Custom Passive Device Authoring (CPDA) flow that Cadence released with Virtuoso Studio IC23.1 provides a comprehensive methodology to create all this data and removes existing verification gaps. After an easy-to-use signature generation flow, a custom passive device can be used like any PDK device through out the entire RFIC design and verification flow without any manual user interaction.

This blog describes the first steps of characterizing a new custom passive device, model generation for circuit simulation, and marker shape creation. In the next blog (Part 2), we will talk about the usage of marker shapes to include custom passive devices for LVS with Physical Verification System (PVS) or Pegasus Verification System and for parasitic extraction with Cadence Quantus Extraction Solution.

Fig. 1 shows the flow diagram for CPDA. The starting point is an optimized device layout. You can create it manually or use a layout synthesis tool like EMX Designer.

Fig. 1: Custom Passive Device Authoring Flow

Once the device layout is completed, we need a symbol view, a device model, and the correct CDF setup to include the device model in a Spectre netlist for circuit simulation. The Virtuoso Electromagnetic Solver Assistant gives access to a flow that automatically generates this data. Fig. 2 shows the definition of a full cellview model for a custom inductor.

Fig. 2: Generation of a new full cellview model in the Electromagnetic Solver Assistant

The user can define ports and send the entire layout to EMX Designer for electromagnetic simulation and S-parameter extraction. Fig 3 shows how extracted S-parameters are used to generate a symbol view and an S-parameter view.

Fig. 3: Generation of symbol and S-parameter views

In addition, all setup information required for Spectre netlisting is stored in the CDF of the custom device. Now, the S-parameter view can be selected in the Hierarchy Editor (HED) for circuit simulation. Refer to a wonderful blog my colleague, Johannes Grad, has written about this topic. 

With these steps, all necessary data for schematic generation and pre-layout circuit simulation is available.

But what about the backend? What about physical verification? How many marker shapes do you have to add to your last custom transformer to enable all the different verification steps? I guess there is a marker shape for device specific DRC rules, another one to exclude the device from metal fill, and some more for other flow steps. And obviously, you need a marker to inform layout extraction tools that the inductor metal is part of a device and not just metal routing.

The new CPDA flow facilitates this tedious task. It provides the possibility to automatically create any number of marker shapes based on a simple user-defined recipe. CPDA supports a large number of Boolean operators, such as AND, NOT, OR, selection operators, such as Inside, Outside, Holes, or sizing operators, such as Grow to derive a new shape from an existing one. Subsequently, you can add the derived shape to the device layout on any existing technology layer. Fig. 4 shows an example of such a recipe to create several marker shapes for a custom inductor.

Fig. 4: Exemplary recipe for automatic marker shape generation with CPDA

With Virtuoso Studio IC23.1, the Electromagnetic Solver Assistant has a new top-level icon to launch the CPDA flow. The first step in this flow is Generate Marker Shapes as it is shown in Fig. 5.

Fig. 5: Generate Marker Shapes with CPDA        

Fig. 6 shows an exemplary result of this step with marker shapes created as defined in the recipe file.                

Fig. 6: Custom inductor with marker shapes

Recipes are stored in the devices.txt file. You can specify multiple recipes in a single file. The example that was used for Fig. 5 included separate recipes for inductors and transformers. The functionality to define marker generation recipes is very flexible, and you can use it for any number of generic devices. It is based on process technology-specific design rules. More information on writing marker generation recipes and how to point the tool to the devices.txt file can be found in the Authoring Custom Passive Devices chapter of the Virtuoso Electromagnetic Solver Assistant User Guide for IC23.1. I’m sure your CAD department will be able to help you with the setup and enablement.

This is the first blog on CPDA. In the next Virtuoso Meets Maxwell blog, we will talk about using auto-generated marker shapes to enable top-level LVS for RF designs with any number of custom passive devices. Today, RF designers use LVS blackboxing or net-splitting metal resistors for this verification step. It's worth another blog to talk about the verification gaps inherent in these approaches, and how to seamlessly these gaps can be closed with CPDA.

Stay tuned! You’ll be excited!

Related Resources

For more information on Cadence circuit design products and services, visit www.cadence.com.

Claudia Roesch

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For any questions, general feedback, or even if you want to suggest a future blog topic, write to custom_ic_blogs@cadence.com.

About Virtuoso Meets Maxwell

Virtuoso Meets Maxwell series includes posts about the next-generation die, package, and board design flow with a focus on reinventing and optimizing the design process to ensure that the designer remains a designer! Keep watching! Subscribe to receive email notifications about our latest Custom IC Design blog posts.