Knowledge Booster Training Bytes: Virtuoso Layout for Advanced Nodes - Quickstart

Advanced node technologies require specific layout designs due to their complicated manufacturing process. These designs have strict device placement and additional constraints, necessitating multiple masks for a single layer on the wafer. A row-based methodology using Snap Patterns (SPs), Width Spacing Patterns (WSPs), and Multiple Patterning tools works best for advanced node processes. In this blog, we will discuss Width Spacing Patterns (WSP) and Multiple Patterning Tools (MPT), the benefits of FinFET, and the challenges associated with its layout.

Width Spacing Patterns

Width Spacing Patterns (WSPs) are used in advanced node designs to create tracks with specific widths and spacing for correct-by-construction track-based routing. Virtuoso Layout Suite supports Width Spacing Patterns (WSP) to create tracks in the layout. WSPs are an advanced form of snap pattern definitions (SPDef) that define the tracks on which shapes can be placed.

Virtuoso Multiple Patterning Technology

Virtuoso MPT helps to visualize how an advanced node layout can be decomposed to mask colors. Virtuoso Multi-Patterning Technology (MPT) is used for multi-patterning lithography, such as Litho-Etch-Litho-Etch (LELE) and Self-Aligned Double Patterning (SADP) and uses different colors to represent up to four masks for each drawn layer. For LELE, the colors directly map to the masks. For SADP, this method effectively determines whether a design can be successfully decomposed during the mask-making step.

                                           LELE                                                                               

                           SADP

At Advanced Process Nodes, CMOS technology is shifting from planar field-effect transistors (FETs) to more advanced device structures that provide better control over short-channel effects and reduced leakage. This has resulted in the emergence of multi-gate FETs, which are also referred to as tri-gate FETs or FinFETs. FinFETs are non-planar transistors, where the gate surrounds the channel or Fin on three sides. 

Custom layout implementation flows for advanced IC processes continue to evolve, addressing many of the productivity challenges of shrinking feature sizes and a growing set of complex design rules. Modern custom layout design relies increasingly on correct-by-construction methodologies to address these productivity gaps and to avoid late design-cycle iterations caused by issues discovered during signoff.

Defining Advanced Node Technology

Advanced node technology in semiconductor manufacturing creates integrated circuits with smaller transistor sizes. Smaller nodes mean higher miniaturization. This technology drives innovation by improving performance, enabling faster switching speeds and lower power consumption. It also allows for more complex designs, paving the way for applications in artificial intelligence, 5G, and IoT.

FinFETs and multi-patterning technologies brought a paradigm shift in how engineers design and manufacture custom and analog circuits. Grid-based placement and track-based routing help layout designers abstract complex design rule check (DRC) rules. GAAFets and backside metal power delivery pave the way for next-wave innovations in design tools and methodologies. FinFET devices can carry a larger current per area than planar CMOS.

FinFET Advantages

• Excellent shut-off
  • Less power
  • Less leakage
• Good ability to drive current
• No doping in the fin (channel area)
  • Less variability

FinFET Layout Challenges:

• Layout impacts design
• Designers can create circuits that can’t be “built” (won’t perform to specification)
• Some restrictions must be forced on the circuit designer
  • The goal is regular and repeated structures
  • Limit the device configurations: allowed fin counts and allowed poly lengths
  • Develop guidelines for using different fin counts and poly lengths in the same circuit
  • The methodology must be in place before design work begins
• Layout productivity and resources required
  • Flow to minimize coloring and DRC errors
  • Area-efficient layout
  • Time-efficient layout

In Conclusion, to address the challenges mentioned, it is recommended to use the Virtuoso layout suite. For advanced node designs, using Width Spacing Patterns (WSPs) to create tracks with specific widths and spacing to enable correct-by-construction track-based routing is best. Virtuoso MPT can be used to visualize how an advanced node layout can be decomposed into mask colors. The snap pattern snapping feature can help to snap instances to suitable grids or snap patterns to ensure better design quality. The Group Array and Array Assistant feature can help to place devices more efficiently, reducing the time taken for the process. Automated dummy insertion can also be used to overcome DRC and layout-dependent effects on the devices, ensuring a more reliable design. Simulation-driven routing is recommended to ensure the proper EM/IR for signal nets to enhance the performance of the design.

Enroll in the Course Virtuoso Layout for Advanced Nodes to learn more about Advanced Process Nodes.

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About Knowledge Booster Training Bytes

Knowledge Booster Training Bytes is an online journal that relays information about Cadence Training videos, online courses, and upcoming webinars that are available in the Learning section of the Cadence Learning and Support portal. This blog category brings you direct links to these videos, courses, and other related material on a regular basis.

Sandeep O

On behalf of the Cadence Training team