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Cadence® Spectre® AMS Designer is a high-performance mixed-signal simulation system. The ability to use multiple engines and drive from a variety of platforms enables you to "rev up" your mixed-signal design verification and take the checkered flag in the race to the market. The Start Your Engines! blog series will provide you with tips and insights to help you tune up your simulation performance and accelerate down the road to productivity.
In the current times, post-layout simulation has become more and more important in design verification, not only in pure transient simulation but also in EM/IR analysis and electrothermal analysis. Usually, designers run a post-layout mixed-signal simulation with a design block (DUT) using a schematic and the rest of the design or testbench using pre-layout schematic or digital functional blocks. However, with a more complex design structure and advanced design flow, people now try to run a post-layout mixed-signal simulation with a more complex configuration. One such example is a sandwich structure, where the DUT block is a DSPF file with a blackbox inside that needs to be replaced by a digital functional block.
There are two advantages of running this type of configuration.
Firstly, it will further speed up the mixed signal post-layout simulation. The traditional blackbox DSPF allows designers to use pre-layout schematic to replace the blackbox in DSPF, but it is still limited by the capability and performance of the analog solver. When using Verilog/Verilog-AMS/SystemVerilog blocks to replace the blackbox in DSPF, it will give more performance gain and allow a much larger scale of the design to simulate.
Secondly, it will allow designers to run verification as early as possible. Usually, post-layout simulations are run at a very late stage of the design flow. However, with more and more IP reuse, designers want to put the physical constraint at an early stage of the design flow and check the brief placement and routing. In this case, the sub-block level may still be at the functional or even behavior level, but designers prefer to run the full design post-layout on the top level to get an early estimation.
With the DSPF-in-the-middle feature available in Virtuoso ADE flow, designers can easily set up this type of configuration in the Hierarchy Editor (HED) and run a post-layout mixed-signal simulation with just a few clicks.
Spectre AMS Designer and Xcelium Simulator Mixed-Signal User Guide
Rapid Adoption Kits (RAKs)
Using DSPF Blackboxes in AMS Simulations for Post-layout Verification
Spectre AMS Designer Product Page
For more information on Cadence circuit design products and services, visit www.cadence.com.
The Start Your Engines series brings you blog posts from several analog/mixed-signal subject matter experts on a variety of topics, such as introduction to the new features in AMS Designer, tips for enhanced working with existing features, and much more. To receive notifications about new blogs in this series, click Subscribe and submit your email ID in the subscription box.
- Qingyu Lin