Start Your Engines: Mixed-Signal Behavioral Modeling Review and Coaching

Cadence^® Spectre^® AMS Designer is a high-performance mixed-signal simulation system. The ability to use multiple engines and drive from a variety of platforms enables you to "rev up" your mixed-signal design verification and take the checkered flag in the race to the market. The Start Your Engines! blog series will provide you with tips and insights to help you tune up your simulation performance and accelerate down the road to productivity.

Bonjour!

In this post, I will cover how the AHDL Linter utility checks analog behavioral code for modules and highlights the possible mistakes in your code for the Verilog-AMS, Verilog-A, SystemVerilog-AMS, and VHDL-AMS languages that could slow down a Spectre AMS Designer simulation. It also suggests the code changes you can apply.

Analog Mixed-Signal Languages

Four AMS languages can be used with Spectre AMS Designer simulator:

• Verilog-AMS, Accelera Standard
• Verilog-A, the analog subset of Verilog-AMS
• SystemVerilog-AMS (Cadence implementation)
• VHDL-AMS, IEEE Standard

These languages are powerful and flexible and let you create customized behavioral models that have an easily readable code that allows you to simulate complex systems without transistor-level implementation. The analog blocks for these modules are computed in the analog solver that resolves non-linear differential equations. The derived calculation is automatically done. This is the beauty of these languages!

Behavioral Modeling Traps

Unfortunately, there are traps in the usage of these languages. For example, your code could introduce very small breakpoints for time step rejections. Conductance discontinuity could also cause Newton convergence failures.

AHDL Linter can be quoted as a system expert for such cases.

How Was This Expert System Created and How Does It Operate?

Cadence has experts and engineers who have taught behavioral modeling in universities and have more than thirty years of experience in analog and mixed-signal behavioral modeling and simulations. These engineers continually help designers to identify modeling code issues in their Verilog-AMS, Verilog-A, SystemVerilog-AMS, and VHDL-AMS behavioral models. Based on this knowledge, a king of expert systems has been implemented in the Spectre AMS Designer Simulator. We call it the AHDL Linter.

It has two operations:

• The static linter reads your code and analyzes it during the compilation stage. It detects possible issues in advance simulations. These issues are reported with the code file name, code lines, and the detailed construct.
• The dynamic linter continuously analyzes the operation of all your behavioral code instances during simulation. If an issue is detected, it is immediately reported to the user.

Which Issues Can the AHDL Linter Detect?

AHDL Linter can detect any code usage that may lead to potential convergence or performance problems. The table below lets you know the type of linter supported for each language.

Usage

AHDL Linter can be enabled during compilation or simulation by selecting the Linter check check box in the Miscellaneous tab of the AMS Options form.

Alternatively, use the xrun command -spectre_args "-ahdllint" to enable the AHDL Linter as shown in the figure below:

If an issue is detected, a warning message is displayed as shown in the figure below.

You can use the ahdlhelp Linux program utility to view the extended help on various messages reported by AHDL Linter. To view the extended help,  provide the AHD Linter ID number as an argument. You can also launch the application utility ahdlhelp AHDLLinterID .  It reports the issues in the coding style and the possible code enhancements. Ahdlhelp prints out code error examples and the suggested fixes. 

Key Benefits

• Ease of use
• Integrated in the Virtuoso and other command-line flows
• Works for simple or complex testcases instantiating Verilog-AMS, Verilog-A modules, SystemVerilog-AMS connect modules, and VHDL-AMS entities or architectures
• Productivity: It highlights the file paths, module behavioral code lines, and constructs that could create issues
• Automation: It automatically checks all the behavioral codes instantiated by AMS modules in your testcase
• Efficiency: The integrated dynamic AHDL Linter identifies any code constructs that are slowing down the simulation
• Improvement: Provides multiple solutions for the identified possible code problem

Conclusion

Check and Improve your Verilog-AMS, Verilog-A modules, SystemVerilog-AMS, and VHDL-AMS behavioral code with the AHDL Linter integrated in Spectre AMS Designer simulator. This is very simple to do!

Designers can analyze and check their behavioral models with the AHDL Linter. It also suggests possible code changes for improving model accuracy, reusability, and portability. The AHDL Linter messages explain where and how the modules can be enhanced.

We have been receiving excellent feedback from the designers and CAD engineers that have enabled it for their simulations. They have been able to improve their behavioral code, discover issues, and finally speed up their verifications.

Hope you are now excited to try it out yourself! If you need more details, contact your Cadence Support team.

Related Resources

For more information on Cadence circuit design products and services, visit www.cadence.com.

About Start Your Engines

The Start Your Engines series would bring to you blog posts from several analog/mixed-signal subject matter experts on a variety of topics, such as introduction to the new features in AMS Designer, tips for enhanced working with existing features, and much more. To receive notifications about new blogs in this series, click Subscribe and submit your email ID in the Subscriptions box.

- Andre Baguenier