Virtuoso Meets Maxwell: Thinking Outside the Chip--Advantages of Interoperability Between Best-In-Class IC and IC Packaging Design and Verification Tools

'Virtuoso Meets Maxwell' is a blog series aimed at exploring the capabilities and potential of Virtuoso RF Solution and Virtuoso MultiTech. So, how does Virtuoso meets Maxwell? Now, the Virtuoso platform supports RF designs, and the RF designers measure the physical and radiation effects by using the Maxwell's equations. In addition to providing insights into the useful software enhancements, this series broadcasts the voices of different bloggers and experts about their knowledge and experience of various tools in the Virtuoso IC-Packaging world along with the nuances of RF, microwave, and high frequency designs. Watch out for our posts on Mondays.

Many of today’s analog, RF, and mixed-signal designs require the integration of multiple ICs across varying substrate technologies to achieve required performance goals. The integration of heterogeneous devices allows designers to achieve results that can’t easily be duplicated using a monolithic IC (SoC) design approach. At the same time, heterogeneous integration introduces a whole new set of challenges for today’s designers.

System in package (SiP) is one of the most common methods of integrating mixed technologies into a single design. This approach requires seamless integration between the IC and package substrate design teams and an integrated tool flow. The Virtuoso MultiTech Framework addresses these challenges with a novel, integrated cross-platform solution that streamlines and automates the design of a package/module featuring off-chip devices and multiple ICs based on differing process design kits (PDKs). 

Cadence^® Virtuoso^® MultiTech Framework links best-in-class IC and IC packaging technologies—the Virtuoso custom IC and Allegro^® IC package design capabilities—creating a holistic methodology that automates and streamlines the design and verification flow for multi-die heterogeneous systems.

Cadence^® Virtuoso^® MultiTech Framework unifies the strengths of the Virtuoso Schematic Editor, Virtuoso ADE Assembler, and SiP Layout Option for IC and IC package/system-level capture, design, implementation, analysis, and verification. In addition, the Virtuoso MultiTech Framework provides an automated interface with Cadence^® electromagnetic solvers. 

Design engineers using the Virtuoso MultiTech Framework capabilities are empowered with capturing the system-level layout interconnect for any number of ICs (chiplets) along with other components comprised in a typical system. This evolutionary approach streamlines the validation of the constructed connectivity of the hierarchical system comprised of ICs, IC packages, and boards. Within a familiar environment capable of pre- and post-layout simulation along with in design layout versus schematic (LVS) check.

The Virtuoso MultiTech Framework utilizes a familiar use model within Virtuoso Schematic Editor to transfer the logic description to SiP Layout Option for physical implementation. The entire flow is automated from library creation, technology file creation and elimination of the highly manual and error-prone process of integrating system-level layout connectivity and parasitic model back-annotation to the golden schematic.

See the related Rapid Adoption Kit.

About Virtuoso Meets Maxwell

Virtuoso Meets Maxwell series includes posts about the next-generation die, package, and board design flow with a focus on reinventing and optimizing the design process to ensure that the designer remains a designer! Keep watching!

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Related Resources

• Virtuoso RF Solution
• Virtuoso MultiTech Framework Guide
• Virtuoso RF Solution Guide
• What’s New in Virtuoso (ICADVM18.1 Only)

For more information on Cadence circuit design products and services, visit www.cadence.com.

Dan Baldwin