Virtuosity: In the Line of Veri-Fire - Episode 1

Hi readers! Welcome to Veri-Fire, a blog series that helps you deep dive into Virtuoso® ADE Verifier and learn about its various whys and hows. In this series, Walter Hartong, a Product Engineering Architect at Cadence, will be answering some frequently asked questions on Virtuoso ADE Verifier. Stay tuned for some interesting explanations and solutions! And if you have any specific questions in mind, feel free to send those to veri-fire@cadence.com. 
You can find most of the questions that come across to Walter on the Virtuoso ADE Verifier FAQ page, and the list might grow, depending on your questions ! 

Analog design verification has been in the works since decades and so far, most of the designs have been taped out successfully, so why would (analog) verification be “in the line of fire (or Veri-Fire)” just now? For the last 20 years, Walter has written countless introductions to papers or talks, covering topics such as an increase in design complexity, shrinking process nodes, and increased complexities because of tighter integration between analog and digital. So, why is it different today?

The pressure comes from three different directions:

Complexity

The core of analog components is still the same as it was 10 years ago – a filter is still a filter – but today, not only the performance requirements have increased significantly, but design blocks have started using different modes of operations. These in turn add up to hundreds of different scenarios that need to be tested, which increases the complexity. Shrinking process nodes push secondary effects such as parameter variation, noise, temperature effects, aging aspects, crosstalk, and the likes in the foreground and mandate specific verification talks. 

Quality 

The requirements in terms of verification quality are increasing. Almost every chip today contains some analog components and a tape-out failure due to problems in the analog portion of the chip is totally unacceptable. There is certainly a specific pressure coming from the automotive and medical standards, as well as the consumer market demanding a lot of documentation, traceability, and quality. There's a good chance that your customer wants the know-how of your design verification.

Alignment 

The complexity and quality trends make the design and verification process much more complicated. A direct consequence is that more people are involved and a coordination between the different teams becomes all the more essential. The chip architect needs to be in close contact with the analog designer; design and layout tasks cannot be done separately anymore; the connection between analog and digital design is essential to get things right. Nobody can afford to run tasks sequentially anymore, resulting in firmware development, analog or digital design and verification, and layout tasks running in parallel and influencing each other.

Walter says that analog verification is “in the line of fire”. It needs our attention and we need to find new ways to more efficiently solve the problems. Along with the new generation of Virtuoso ADE products - Virtuoso ADE Explorer and Virtuoso ADE Assembler, we have also released Virtuoso ADE Verifier earlier, which focuses on managing and coordination of verification tasks. Many of you have heard about Virtuoso ADE Verifier or have it in use already but there are still a lot of unanswered questions, and this blog will try to answer those. If you have more questions which we should answer, please feel free to send them over and we will give it a shot.

In today's post, the spotlight is on the beginner-level questions, for example, from those of you who want to become end-users of Virtuoso ADE Verifier, but haven't explored its potential yet, or users who want to learn more about it. Let's take a look at all that's covered in this post of Veri-Fire:

Steve: I'm completely new to Virtuoso ADE Verifier. Can you summarize what the tool is good for?  I have been using Spectre technology and Virtuoso ADE Explorer/Virtuoso ADE Assembler. What else do I need?

Walter: Can you remember a situation in the team where the status of the overall verification task was unclear? Have you seen cases where spec values were unclear or changed? I'm sure you haven't - but believe me it happens for all other designers out there every day. Virtuoso ADE Verifier is a tool that brings all the information together – the requirements including the spec values, the connection to your Virtuoso ADE Assembler sessions, and the results and the status of your verification. You can certainly achieve similar things with MS Excel tables, but it is a lot of manual work and it is hard to keep the table up to date. Virtuoso ADE Verifier is part of the Virtuoso ADE Product Suite and thus has access to all the information you need without manual intervention.

Well, if you are working alone most of the time, it isn't that big a problem. You know what you need to do, and you know the status. But the larger the team gets, the harder it is to keep track of all the people and the overall status. Hope that helps!

Pradeep: I hear that Virtuoso ADE Verifier adds value mostly for automotive type projects but I'm not into the automotive industry. Can Virtuoso ADE Verifier still help me in some way?

Walter: Check out the video here. 

Bob: What are "Requirements" or "Implementations"? Can you clarify the terminology?

Walter: Let's start with implementations. Implementations are Virtuoso ADE Assembler views which you already have. You can bring in 10, 20, or even 50 Virtuoso ADE Assembler views into one Virtuoso ADE Verifier session to have them all under control at the same time. You will see that Virtuoso ADE Verifier lists all the tests and expressions and specs of all the implementations.

Requirements are what the term says – all the requirements of your verification. These could be specs from the customer, internal specs, and any other requirements you might have.

I'm guessing your next question: Why separate implementations and requirements? Isn't this one and the same thing?

Yes and no. In many cases, requirements and implementations have a 1:1 mapping and they follow the same structure. But if you think about the big picture, it makes sense to separate the two. Assume that you have 50 implementations in your Virtuoso ADE Verifier session with 10 tests each and 20 outputs per test. This gives you 10,000-line entries in the Implementations pane. Do you really want to check 10,000 results at this level? You probably can skip half of the results anyways because often not all the results are important for the overall verification progress. You may want to structure this information better and your requirements can help with this.

Also, think about re-use and top-down. In the next project, there is a good chance that you may want to reuse the structure of your requirements. We should talk about top-down at some point in more detail.

We hope you learned something new in this episode of Veri-Fire. Keep the questions coming!  
Also, do check out the Related Resources section for more details. 

Related Resources

For more information on Cadence circuit design products and services, visit www.cadence.com.

About Virtuosity

Virtuosity has been our most viewed and admired blog series for a long time. The series has brought to the fore some less well-known yet very useful software and documentation improvements and has also shed light on some exciting new offerings in Virtuoso technology. This series broadcasts the voices of different bloggers and experts, who continue to preserve the legacy of Virtuosity and try to give new dimensions to it by covering topics across the length and breadth of the Virtuoso environment, and a lot more. To receive notifications about the new blogs in this series, click Subscribe and submit your email ID in the Subscriptions box.

Happy reading, and stay safe!

Team ADE Verifier