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Cutting-edge innovation…Top-down planning…Reliable and formalized verification…Scalable performance!
These are the current buzzwords floating around in the electronic design automation industry. In fact, these buzzwords and more describe the new release of Virtuoso^® ADE Verifier in IC6.1.8 and ICADVM18.1. Analog verification methodology is ever-changing. With the introduction of very large and complex verification project setups involving multiple users, the verification standards and market pressure require much more from the software. Verifier is a comprehensive application that performs plan-based verification of analog and mixed-signal designs. The latest IC release of Verifier brings much anticipated improvements that any verification manager will relish.

The internal architecture for Verifier has been upgraded to take performance, speed, and verification to the next level. The illustration below describes the high-level data structure of the new Verifier flow.

To support these architectural enhancements, we have made the following improvements:

• Performance: Improved performance enables faster verification of larger and more complex designs.
• Simulation Planning and Coverage Environment: Introduction of the Setup Library Assistant (SLA) in ADE Assembler and ADE Verifier enables planning and creation of project-specific master setups. In ADE Assembler, you can quickly and efficiently create setups at the test level using these master setups. In ADE Verifier, you can verify the top-to-down progress of your design by comparing the implementation histories with defined operating conditions from the master setups and reviewing the progress of your design based on the reported Analog Coverage percentage.
• Cellview Updates: On-demand updates, file based-monitoring, and the absence of update loops help in increasing performance.
• Sharing of Data: Direct sharing of data with ADE Assembler is now possible.
• UI Responsiveness: More responsive UI with intuitive forms, menus, and toolbars make the interface more user-friendly than ever.
• External Cellviews: Refashioned external reference flow to support unidirectional references to multiple Verifier cellviews provides a multi-level hierarchy, allowing more flexibility for designers, and the latest verification status to the project manager.
• SKILL Functions: New and improved task-oriented SKILL functions are now available.
• Flows: Improved flows for new assistants and filters, together with flows for exporting and importing CSV, Excel, and mapping files.
  
  Try out the brand-new Verifier in IC6.1.8 and ICADVM18.1 to know how you can do more with your design project verification!

Related Resources

• Rapid Adoption Kits

  • Virtuoso ADE Verifier
  • Virtuoso ADE Explorer and Virtuoso ADE Assembler
  • Setup Library Assistant in ADE Assembler and Verifier 
  • Virtuoso ADE Assembler Run Plan Assistant

• Videos

  • Virtuoso ADE Verifier Basic Flow
  • Setup Library Assistant in ADE Verifier
  • Simulation Planning and Coverage Environment - Setup Library Assistant

• Blog

  • Simulation Planning and Coverage Environment - Introduction

• User Guides

  • Virtuoso ADE Verifier User Guide
  • Virtuoso ADE Assembler User Guide

For more information on Cadence circuit design products and services, visit www.cadence.com.

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Happy Reading!

Rashmi Girdhar