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Cutting-edge innovation…Top-down planning…Reliable and formalized verification…Scalable performance! These are the current buzzwords floating around in the electronic design automation industry. In fact, these buzzwords and more describe the new release of Virtuoso® ADE Verifier in IC6.1.8 and ICADVM18.1. Analog verification methodology is ever-changing. With the introduction of very large and complex verification project setups involving multiple users, the verification standards and market pressure require much more from the software. Verifier is a comprehensive application that performs plan-based verification of analog and mixed-signal designs. The latest IC release of Verifier brings much anticipated improvements that any verification manager will relish.
The internal architecture for Verifier has been upgraded to take performance, speed, and verification to the next level. The illustration below describes the high-level data structure of the new Verifier flow.
To support these architectural enhancements, we have made the following improvements:
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