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Yagya Mishra
Yagya Mishra
31 Jan 2019
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Virtuosity: Simulation Planning and Coverage Environment (SPACE)- Introduction

Complexity in Analog designs is increasing rapidly as technology is shrinking beyond 28 nanometers. Such complexity leads to a huge list of operating conditions (Process, Voltages and Temperatures often referred as PVTs) that must be considered during simulation to have confidence over your circuit performance and to be sure that all the different design blocks designed over the same technology node will work okay when chipped together.

And that brings another challenge for Project Managers who have the responsibility to sign-off different design blocks. Often, a team assigned to design an Analog block divides the design requirement into sub-blocks and assigns the designing of each sub-block to individual engineers. Project Managers are then required to make sure that all the design blocks are simulated on the correct sets of corners, voltage values, and are using the appropriate version of model files.

In the IC6.1.8 release, Virtuoso® ADE Assembler and Virtuoso® ADE Verifier have a new assistant called the Setup Library Assistant (also referred to as SLA) that allows Project Managers to:

  • Define, create, maintain and share project specific (common) master setup that includes multiple groups of sweep variables, corners, model files and so on.

  • Save the specified setup in a cellview independent of the maestro view.

  • Use the defined operating conditions (Verification Space) in ADE Verifier as a requirement to measure the overall Analog Coverage (operating conditions that have been missed out during simulation).

ADE Verifier reports the completeness of project based on 'Analog Coverage'.

To see the theory behind the Setup Library Assistant in more detail, check out the videos in the reference section below. Or download the RAK to try this out for yourself. 

Related Resources

Rapid Adoption Kit

  • Setup Library Assistant in ADE Assembler and Verifier

Videos

  • Setup Library Assistant in ADE Assembler
  • Setup Library Assistant in ADE Verifier
  • Simulation Planning and Coverage Environment - Setup Library Assistant

User Guide

  • Virtuoso ADE Assembler User Guide - Working with the Setup Library Assistant
  • Virtuoso ADE Verifier User Guide - Verifying the Design Against the Specified Setup

For more information on Cadence circuit design products and services, visit www.cadence.com.

About Virtuosity

Virtuosity has been our most viewed and admired blog series for a long time that has brought to fore some lesser known, yet very useful software and documentation improvements, and also shed light on some exciting new offerings in Virtuoso. We are now expanding the scope of this series by broadcasting the voice of different bloggers and experts, who would continue to preserve the legacy of Virtuosity, and try to give new dimensions to it by covering topics across the length and breadth of Virtuoso, and a lot more… Click Subscribe to visit the Subscription box at the top of the page in which you can submit your email address to receive notifications about our latest Virtuosity posts. Happy Reading!

Yagya D Mishra

  • verifier
  • PVT
  • coverage
  • Analog Coverage
  • Analog Simulation
  • Virtuoso Analog Design Environment
  • space
  • Custom IC Design
  • Assembler
  • verification

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