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Complexity in Analog designs is increasing rapidly as technology is shrinking beyond 28 nanometers. Such complexity leads to a huge list of operating conditions (Process, Voltages and Temperatures often referred as PVTs) that must be considered during simulation to have confidence over your circuit performance and to be sure that all the different design blocks designed over the same technology node will work okay when chipped together.
And that brings another challenge for Project Managers who have the responsibility to sign-off different design blocks. Often, a team assigned to design an Analog block divides the design requirement into sub-blocks and assigns the designing of each sub-block to individual engineers. Project Managers are then required to make sure that all the design blocks are simulated on the correct sets of corners, voltage values, and are using the appropriate version of model files.
In the IC6.1.8 release, Virtuoso® ADE Assembler and Virtuoso® ADE Verifier have a new assistant called the Setup Library Assistant (also referred to as SLA) that allows Project Managers to:
Define, create, maintain and share project specific (common) master setup that includes multiple groups of sweep variables, corners, model files and so on.
Save the specified setup in a cellview independent of the maestro view.
Use the defined operating conditions (Verification Space) in ADE Verifier as a requirement to measure the overall Analog Coverage (operating conditions that have been missed out during simulation).
ADE Verifier reports the completeness of project based on 'Analog Coverage'.
To see the theory behind the Setup Library Assistant in more detail, check out the videos in the reference section below. Or download the RAK to try this out for yourself.
For more information on Cadence circuit design products and services, visit www.cadence.com.
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Yagya D Mishra