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Shrinking size of ICs and highly complex layouts containing billions of transistors and miles of interconnects....all of this doesn't sound new now. The industry has been pretty fast in adopting advanced node designs and has witnessed various innovations to overcome the challenges faced at this level. One of the challenges is accurate and timely analysis of the effects of electromigration (EM) and IR drop, and faster clearance of physical verification of transistor-level designs.
In-design electromigration analysis, a unique feature of Virtuoso® Electrically Aware Design flow, helps you address this challenge. This feature uses the electrical constraints saved as part of the design, and the electrical data saved as part of the simulation results generated by Virtuoso ADE Explorer or Virtuoso ADE Assembler to run EM and IR drop checks while creating layouts in Virtuoso Layout Suite. As you can identify and resolve electrical issues early in the design cycle, you can create electrically correct layouts approximately 30% faster than the old design flow in which EM checks were run after completing the layout.
If you haven't moved to the Virtuoso Electrically Aware Design flow yet, read further to know more about the features of this flow and how you can benefit from them.
EM extraction in Virtuoso Layout Suite is powered by an in-design parasitic extraction engine that you can run on demand for selected nets, or for a partial or complete layout. No need to wait for a layout that is LVS-clean (that is, when the Layout versus Schematic check resulted in no major violations). Just select the critical nets on the layout and extract all interconnect parasitics (resistance, capacitance, and coupling capacitance) affecting those nets in the layout.
With these parasitic details, you can run EM checks and analyze how well the nets meet the electrical constraints defined by the circuit designers.
For interactive analysis, you can enable highlighting of EM violations or heat maps on the layout using predefined color maps, and then cross probe the EAD Browser and layout to quickly spot and fix the issues. The details of violations can also be seen in the tooltips.
The following figure shows an example of EM violations highlighted on the layout canvas:
While you are drawing or redrawing the wires to resolve the reported violations or to complete the layout, you would want to ensure that the changes are correct. A quick access to the resistance and capacitance, EM violations, and the maximum current carrying capability of a wire can be very helpful in making decisions. For this, you can use the point-to-point info balloons to interactively view EAD parameters for the segments between any two points in the layout.
The following figure shows an example of an info balloon between two points selected on a net:
As the parasitic data is readily available before the layout is complete and LVS clean, circuit designers can resimulate the design using the partial layouts to check whether the design specs are met. If required, they can make design modifications and ensure that the specifications are met with layout effects. Therefore, design verification can happen early in the design cycle thereby reducing the overall development time.
So, enough reasons to see how you can benefit by these capabilities offered by the Electrically Aware Design flow. Do try it!
Rapid Adoption Kits:
For more details, refer to Virtuoso Electrically Aware Design Flow Guide.
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Namrata Malhotra, with inputs from Sankalp Srivastava