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Here’s a line of thought that we’ve probably never considered: We’re like a river. We go through life taking the path of least resistance. We all do – all human beings and all of nature. We tend to take the easy way out in life – in our actions and in our choices. We’re constantly on the lookout for ways that lead us to a better, easier, and happier life. And, this holds true for our work and workplace as well. Let’s see how.
As design engineers, don’t you think your life would be easier if you discovered the path of least resistance for the devices of your design much ahead of your power planning? Don’t you agree that such foresight would lead you to avoid any potential problems in the later stages of your design flow? If you agree and are willing to have such an experience, I suggest you explore the 'least-resistive path (LRP) analysis' feature in our power integrity tool, Voltus-Fi Custom Power Integrity Solution. This is a long-standing feature of the tool, but its amazing benefits are worth mentioning again.
Power integrity is vital in the successful creation of system-on-a-chip (SoC) designs. Excessive voltage drop (IR) and ground bounce can create timing problems. Also, excessive current can cause electromigration and related thermal effects, leading to chip failures. Solid power-integrity planning and analysis help prevent these problems, and undoubtedly, the best suggestion is to start as early as possible. LRP analysis supplies a useful starting point for evaluating all the instances in your design. It helps you identify the weakly connected devices to the power grid that would create problems later in the flow. It highlights the current path between the selected instance and its voltage source, and displays the worst IR violations along the least-resistive path. Thus, you can fix the violations at a very early stage of the flow.
There are many good reasons why I think you should begin using this feature, if you have not done so already.
You can run LRP analysis in Voltus-Fi Custom Power Integrity Solution in the following two ways:
The following diagram shows how you can run LRP analysis in the GUI mode.
The LRP plot calculates the total resistance between an instance pin and its voltage source along the least-resistive path. If an instance has multiple power pins connected to the power grid, the LRP plot uses the pin with the worst (highest) resistance value to plot the instance-based data. A long path usually indicates a high resistance and potentially high voltage drop. Thus, using this feature, you get to know about the worst IR drop violations in your design.
The figure below shows how the LRP of an instance appears on the layout.
So, now that you know about the hows and whys of LRP analysis, I strongly urge that you give it a try. I'm hopeful that this feature will help you find the path of least resistance to transform your design to be exactly what you want it to be – a clean, violation-free design.
Along with this, you can also explore another important debugging feature of Voltus-Fi Custom Power Integrity Solution, what-if or ECO analysis, which I talked about in my last blog post.
Happy reading, and stay safe!- Pallabi Roy
Voltus-Fi Custom Power Integrity Solution L User Guide
Voltus-Fi Custom Power Integrity Solution XL User Guide
Plotting the Least Resistive Path (LRP)
For more information on Voltus-Fi Custom Power Integrity Solution, visit www.cadence.com.
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