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Arja H
Arja H

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Virtuoso Analog Design Environment
Custom IC Design
Assembler
ADE Assembler

Virtuosity: Preventing Redundant Simulations

1 May 2018 • 3 minute read

I'm sure we all might have come across this situation - not being sure if something has changed in the simulation setup or design so you need to run a new simulation in Virtuoso ADE® Assembler to check the results.  This simulation run may take hours or even days to complete and it's a sheer waste of time when you realize the results are identical to the previous simulation. It gets even worse when you have a regression setup where simulations run to ensure all results are up-to-date. You certainly would not want to spend compute resources and licenses if things are identical.

The tricky question is how to find out that a simulation run is redundant. It is not a trivial task to check all dependencies for a simulation.

To address this issue, starting from IC6.1.7 ISR19 and ICADV12.3 ISR19, a new cdsenv has been provided that allows you to run simulation only if the design, simulation setup or simulation files have changed. 

The variable is off by default.  To enable it, you need to specify the run modes that should run this check in the string parameter.

envSetVal("maestro.simulation" "runModesForIdenticalHistoryCheck" 'string "SRSC MC")

In this example the run modes 'Single Run, Sweeps and Corners, and Monte Carlo' have been set. 

When this variable is set, the Enable reporting of identical histories check box in the Run Options form is enabled. You can select other available options to control the scenarios you would like to check before running a simulation. The ADE Assembler setup will check things like variables, parameters, corners, test setup and run another simulation only if these settings have changed between runs.

Selecting design will check if the schematic or config has changed. Simulation files will check if the model files, include path or simulation files have been changed. Note: it isn't quite clever enough to know if you've changed the content of any model files.

If nothing has changed you will get a pop up like this asking if you really want to run simulation again with the same setup.

This is a handy feature, but really comes into its own when running regressions.

If you're wondering how to ensure that the answer is correct and you don't need to run the simulation again. Well, we are quite sure, but we know it is not a 100% solution and it never will be. There is always the possibility that a tool version has changed, an include file in a model file has changed, or there's a new UNIX environment variable setting -  all these things are not checked. But, don’t panic – if you use the feature in a practical way it can be a great benefit to you. For example, when using a regression setup, it might be good to run the simulation on weekdays with the Enable reporting of identical histories option selected and over the weekend you could run everything by turning this off.

This feature is also integrated in Virtuoso ADE® Verifier, where it can be used to setup regression runs easily.

Related Resources

  • User Guide
    • Virtuoso ADE Assembler User Guide
    • runModesForIdenticalHistoryCheck

For more information on Cadence circuit design products and services, visit www.cadence.com.

About Virtuosity

Virtuosity has been our most viewed and admired blog series for a long time that has brought to fore some lesser known, yet very useful software and documentation improvements, and also shed light on some exciting new offerings in Virtuoso. We are now expanding the scope of this series by broadcasting the voice of different bloggers and experts, who would continue to preserve the legacy of Virtuosity, and try to give new dimensions to it by covering topics across the length and breadth of Virtuoso, and a lot more… Click Subscribe to visit the Subscription box at the top of the page in which you can submit your email address to receive notifications about our latest Virtuosity posts. Happy Reading!

Arja


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