Get email delivery of the Cadence blog featured here
This has been an age old problem, you extract your design and get a DSPF file, then you want to run simulation in Virtuoso® ADE Assembler, or Virtuoso® ADE Explorer, using that DSPF file, but you find that none of your expressions evaluate. That's because the design is flat in the DSPF file, plus the extractor probably added prefixes to devices, changed the finger delimiters and changed the case of nets etc. You probably ended up editing the expressions manually to match, which is tedious. We have been working on a flow to address this issue and now you can use the same expressions in your pre- and post-layout simulations. There is a little bit of manual set up to do first, but the Rapid Adoption Kit, Working with DSPF files in Post-layout Flows in ADE Explorer and Assembler, will explain the steps.
The RAK also explains how to model specific cells in the design as blackboxes. The expressions will work seamlessly even when there are blackboxes as they just revert to the schematic naming scheme.
If you have several DSPF files that you want to sweep, then we have an official flow for that now, again the RAK guides you through the process.
Finally, for pre- or post-layout simulations, voltages on the terminals of devices can be saved or plotted from the ADE outputs, or from Direct Plot.
Virtuosity has been our most viewed and admired blog series for a long time that has brought to fore some lesser known, yet very useful software and documentation improvements, and also shed light on some exciting new offerings in Virtuoso. We are now expanding the scope of this series by broadcasting the voice of different bloggers and experts, who would continue to preserve the legacy of Virtuosity, and try to give new dimensions to it by covering topics across the length and breadth of Virtuoso, and a lot more…To receive notifications about new blogs in this series, click Subscribe and submit your email ID in the Subscriptions box. Happy Reading!