Get email delivery of the Cadence blog featured here
Hello, dear readers!Continually improving the productivity of design engineers is central to the strategy followed by Cadence and has led to a variety of innovations and improved features across our products. Cadence has also actively focused on ways to enable design engineers to leverage and reuse solutions within its different products, thereby streamlining the design flow as much as possible. Recently, Cadence continued these efforts by amalgamating and enhancing multiple products to introduce the ‘Virtuoso EMIR analysis flow for DSPF’ for analog signoff EMIR. Splendid news, isn’t it? Read on to know more…Introduced in IC6.1.8/ICADVM20.1 ISR15, the Virtuoso EMIR analysis flow for a Detailed Standard Parasitic Format (DSPF) file has been designed for analog and RF engineers who are interested in performing EMIR analysis while staying wholly within the Virtuoso environment. As we mentioned earlier, the flow consists of multiple products:
Some key benefits of the flow include:
There are many anecdotal accounts from our users that illustrate the effectiveness of this flow in improving your productivity at work. To quote a few:
“This new flow provides the same-day setup as opposed to the earlier four-day manual setup and debug”.
“It provides more visibility to the layout reliability issues”.
“It adds more confidence for circuit reliability while staying within the familiar Virtuoso environment”.
And the list goes on...
Let us now show you what the Virtuoso EMIR analysis flow for a DSPF file is all about and how it works. In this flow, you can run EMIR analysis with a DSPF file through the Virtuoso interface. You can use this flow to analyze electromigration, voltage drop, and self-heating effects even in advanced process nodes. The flow comprises three steps:
Now that you are familiar with the flow, we suggest you try it with your design and let us know your feedback. To understand how to run each step of the flow, refer to the Virtuoso EMIR Flow for DSPF RAK available on the Cadence Support portal.
Happy reading, and stay safe!- Travis Tiedge, Harsha Hakkal, and Pallabi Roy
Voltus-Fi Custom Power Integrity Solution XL User Guide
Rapid Adoption Kit
Virtuoso EMIR Flow for DSPF
For more information on Cadence circuit design products and services, visit www.cadence.com.
For any questions, general feedback, or even if you want to suggest a future blog topic, write to firstname.lastname@example.org.
Virtuosity has been our most viewed and admired blog series for a long time. The series has brought to the fore some less well-known, yet very useful software and documentation improvements and has also shed light on some exciting new offerings in Virtuoso. We are now expanding the scope of this series by broadcasting the voices of different bloggers and experts, who will continue to preserve the legacy of Virtuosity and try to give new dimensions to it by covering topics across the length and breadth of Virtuoso, and a lot more. To receive notifications about the new blogs in this series, click Subscribe and submit your email ID in the Subscriptions box.