Virtuosity: Conserve Power—A Preamble to Virtuoso Power Manager

‘Conserve Power' is a series of blogs that gives a sneak peek into the world of low power verification. It uncovers the functionality and potential of Virtuoso Power Manager, which lets you specify and manage the power intent for your designs. Watch out for our posts in this miniseries every Thursday between now and Christmas.

Power consumption has always been an overriding concern in electronic design. Consumption relates not only to the power used in the circuitry, but also involves monitoring the circuit to prevent overheating. The battery life of any electronic product can be a deciding factor in its success. Designers are continually devising innovative methods to ensure minimal power consumption without impacting the performance of their designs.

Shrinking technology nodes have been accompanied by an exceptional growth of analog, power management, and RF integration in modern-day mixed-signal systems-on-chip (SoCs). The complexity in terms of architecture and active power management involves multiple operating voltages and power domains, large numbers of operating power modes, and complex supply networks across power domain interfaces. The IEEE 1801 low power standard lays out guidelines to help designers create robust, reliable, and power-efficient designs and accurately specify the power intent of a design in a standard Unified Power Format (UPF).

It is equally important to verify the power efficiency of a design before it is converted into a product to ensure that a defective product does not reach the market. It is a classical low power design technique to power off (isolate) some areas of a design that are not currently needed in order to preserve energy. Multi-voltage considerations in designs also require appropriate handling. This is done with the help of different low power design elements (level shifters, isolation, power switches) at various design interfaces by defining the power intent of the designs. During verification, these low power design techniques used in the design architecture are checked against the specified power intent (UPF).

The most obvious questions a designer might ask are:

• Is there an automated way to write the power intent of a complex hierarchical design in a standard format?
• Power intent and formal verification rings a bell for digital designs, but what about analog designs? 
• Simulation is the most accurate and ideal method of verification, but I have so many power modes to deal with, will I be able to meet the deadline?

Virtuoso Power Manager, launched in the ICADVM20.1 release, provides an interface to specify, import, and export low power intent for designs. It lets you perform static low power verification on designs by using Conformal Low Power and supports analog, digital, and mixed-signal implementations.

Virtuoso Power Manager also addresses the need for creation and verification of power-efficient designs, including validating power intent changes during IP authoring. It provides the capability to annotate the design's power intent-related issues on the schematic; therefore, facilitating the timely correction of power-related violations in the design. You can capture the power intent for the design (including its sub-modules) and map the power domains of an IP block with the domains of the designs. This helps in integrating an IP into the design.

So, what can be done by using Virtuoso Power Manager?

• If the power intent for a design is available in IEEE 1801 format, you can import it to update the design’s power connectivity as per the specified power intent.
• You can check and validate the power intent changes during IP authoring by using the In-Design Checks feature.
• You can automatically extract the power intent of digital, analog, and mixed-signal designs.
• You can export the power intent of the IP design in the standard IEEE 1801 format, which can be further utilized by the SoC verification team for full-chip low power verification.
• As a sign-off, you can verify that the power intent has been implemented correctly when the design is completed. This is done using static verification by Conformal Low Power.
  

This is just a prelude to what will be contained in the future blogs of this miniseries.

What's Next?

Stay tuned to find out about the following topics in the upcoming blogs!

1. Setting up Virtuoso Power Manager   
2. Running In-Design Checks
3. Importing and Exporting Power Intent
4. Verifying a Design using Conformal Low Power
   
   

Happy reading, and stay safe!

Sachin Bhasin and Deepti Mishra Gupta

Related Resources

Virtuoso Power Manager User Guide

For more information on Cadence circuit design products and services, visit www.cadence.com.

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Virtuosity has been our most viewed and admired blog series for a long time. The series has brought to the fore some less well-known yet very useful software and documentation improvements and has also shed light on some exciting new offerings in Virtuoso. This series broadcasts the voices of different bloggers and experts, who continue to preserve the legacy of Virtuosity and try to give new dimensions to it by covering topics across the length and breadth of Virtuoso, and a lot more. To receive notifications about the new blogs in this series, click Subscribe and submit your email ID in the Subscriptions box.