Virtuoso IC6.1.7 ISR22 and ICADV12.3 ISR22 Now Available

3 Sep 2018 • 2 minute read

The IC6.1.7 ISR22 and ICADV12.3 ISR22 production releases are now available for download at Cadence Downloads.

For information on supported platforms, compatibility with other Cadence tools, and details of issues resolved in each release, see:

The links above are functional at the time of publishing. If you encounter any links that are now obsolete, visit https://downloads.cadence.com and select the release name you are interested in to access the related files.

Here is a listing of some of the important updates made to IC6.1.7 ISR and ICADV12.3 ISR over the last few releases:

Faster Netlist Generation for Analog Components in a Mixed-Signal Design (from ISR22)
Use the new Create spectre subckt for extracted view check box to generate an optimized netlist for analog components in a mixed-signal design. Not only does the new option improve the netlisting performance but it also skips the mixed-signal elaboration step for these cellviews, saving the overall simulator processing time.
Default Application to Open a Saved ADE State (from ISR21)
Specify the default application where you want to open a saved ADE state. Use these while migrating to ADE Explorer or ADE Assembler.
Wildcard Syntax for Saving PCells in Netlist (from ISR21)
Use wildcards to specify PCell operating point parameters on the Save Options form.
(ICADV12.3 Only) Display of Packet Name for WSP Tracks in Virtuoso Width Spacing Patterns (from ISR19)
Use custom display packets for WSP tracks.
New Single Schematic Driven Simulation and Layout Flow in Virtuoso System Design Platform (from ISR19)
Use a master schematic to drive both pre- and post-layout simulations and to create the package layout.

For more details on these and all the other new and enhanced features introduced in this release, see:

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Virtuoso Release Team