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The IC6.1.8 ISR12 and ICADVM18.1 ISR12 production releases are now available for download at Cadence Downloads.
For information on supported platforms, compatibility with other Cadence tools, and details of key issues resolved in each release, see:
The above links are functional at the time of publishing. If you encounter any links that are now obsolete, visit https://downloads.cadence.com and select the release name you are interested in to access the related files.
Here is a listing of some of the important updates made to ICADVM18.1 ISR12 and IC6.1.8 ISR12 releases:
Electrically-Aware Pin Sizing (Virtuoso Layout Suite EXL)Identify pins that do not meet the electrical requirements of a design and resize these pins to fix violations using the Electrically Aware Pin Sizing form.
Deep Hierarchy Editing (Virtuoso Layout Suite EXL)Enable deep hierarchy editing to view and edit the layout hierarchy directly from the top-level.
Automatic Hierarchy Generation (Virtuoso Layout Suite XL)Use the Auto Generate Hierarchy command to generate layouts for the entire schematic hierarchy, with instances placed and pins positioned at every level in the hierarchy.
Substrate Layers in Stackup (EM Solver Assistant)Specify any number of substrate layers in a stackup by using the substrate tag in the .emproc files. Earlier, you could specify only up to two substrate layers.
IC6.1.8 and ICADVM18.1
Resource Estimation for LSCS (Virtuoso ADE Assembler and Virtuoso ADE Explorer) Estimate resources required to run simulation for a corner either for all tests or for a specific test. While running resource estimation based on a history, the tool now uses the maximum memory and CPU requirements found across all points.
Setup Library Assistant Functions (Virtuoso ADE Assembler and Virtuoso ADE Verifier)Use the SKILL functions to work with the Setup Library Assistant (SLA) in either nograph or non-GUI mode. These functions help you edit, delete, and read SLA components.
Reliability in ADE Verifier (Virtuoso ADE Verifier)Use the options in the Reliability Outputs group box to view reliability outputs in implementations and verify whether the design degradation is according to the verification plan.
For more details on these and all the other new and enhanced features introduced in this release, see:
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Virtuoso Release Team