'Virtuoso Meets Maxwell' is a blog series aimed at exploring the capabilities and potential of Virtuoso RF and Virtuoso MultiTech. So, how does Virtuoso meet Maxwell? Now, Virtuoso supports RF designs, and the RF designers measure the physical and radiation effects by using the Maxwell's equations. In addition to providing insights into the useful software enhancements, this series broadcasts the voices of different bloggers and experts about their knowledge and experience of various tools in the Virtuoso IC-Packaging world along with the nuances of RF, microwave, and high frequency designs. Watch out for our posts on Mondays.

You heard it right! Virtuoso now supports Package and Board level designs; therefore, it has capabilities to import/create Package PDKs and libraries in Virtuoso. I have been working at Cadence for the past five years, in four out of these five years I have been mainly focused on our Intelligent System Design Solutions for High-Speed and RF Designs, specifically on how to create and maintain Package PDKs in Virtuoso.

Having said all of that, I’m going to share my knowledge as a librarian with you in a multiple blog miniseries. Let’s first start with the library elements that we are currently dependent mainly on Allegro/SiP to create and then use the import mechanism to bring the Package technology and some of the off-chip components into the Virtuoso environment.

As of today, we are relying heavily in Allegro/SiP to create the following:

• Defining the Package Technology Layers (including the wire bond profile info)
• Defining the Package Constraints
• Defining the padstacks for Via, Die Bumps, BGA Balls, etc.
• Creating BGA/LGA/PGA/etc.

Assuming that you know how to take care of these items in Allegro/SiP or you have a Packaging team who does this for you, we can focus on how to import the Allegro/SiP database to Virtuoso to create and maintain the Package PDK/Library. Follow me as I show you how this is done in the following simple steps:

Step 1- Launch Virtuoso ICADVM181 and from the Command Interpreter Window (CIW) go to File >> Import >> From Allegro. It opens the Import Allegro File form.

Step 2- Now we need to select the Allegro/SiP file and under Layout Generation, select the Add Symbol cellView for new BGA Components check box. Then, we click OK to start translation and exit the form.

Step 3- Check the CIW to track the translation. It may take about a minute or so for the translation to begin and complete. Once the translation is finished, we should see the following messages:

Step 4- Now that the import is done, we can take a closer look at what got imported by checking the Library Manager (in the CIW, click Tools >> Library Manager). In this example, we can see a library called PADMODULE_BGA_FC_VRF_example containing the following cells:

• PADMODULE_BGA_FC_VRF_example: Virtuoso layout version of your SiP layout
• BGA17: Schematic symbol you will use in your package design
• BGA: BGA ball pad with layer definitions from SiP
• VRFBUMP2, VRFBUMP2_SHIELDED: Package bump pads with layer definitions from SiP

That’s all it takes to create a Package Library. Through the process of import, the package Technology and Constraints also got imported to Virtuoso. There are multiple ways to prove this to you, by performing either of the following checks

Check 1- We can simply check what technology file your newly created library is attached to, just go to CIW >> Tools >> Technology File Manager and then do a Graph or Dump on your Library. In this case I did a Graph and we can see that Library is attached to itself, which means that it contains the technology file within the library which was imported from SiP:

Check 2- Another simple way to check is to open up the Package layout that was imported and check on the Package Technology layers under the Layer Palette:

To conclude this episode of Package PDK/Library creation, as you can see, in a few simple steps we were able to import the Package data from Allegro/SiP and create Virtuoso libraries to get started on our Package design within Virtuoso environment. Like all the other Virtuoso Libraries/Cells/Views, all these libraries can be Design Managed and can be maintained throughout the design flow. Please follow my Blog for the upcoming episode on how to create Surface Mount Devices (SMD) libraries within Virtuoso.

Related Resources

• Virtuoso RF Solution
• What’s New in Virtuoso (ICADVM18.1 Only)

For more information on Cadence circuit design products and services, visit www.cadence.com.

About Virtuoso Meets Maxwell

Virtuoso Meets Maxwell series includes posts about the next-generation die, package, and board design flow with a focus on reinventing and optimizing the design process to ensure that the designer remains a designer! Keep watching!

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Sanam Vakili