Virtuoso Meets Maxwell: Unified Libraries — Making Way For Cross-Platform Flows

24 Aug 2020 • 6 minute read

'Virtuoso Meets Maxwell' is a blog series aimed at exploring the capabilities and potential of Virtuoso RF Solution and Virtuoso MultiTech. So, how does Virtuoso meets Maxwell? Now, the Virtuoso platform supports RF designs, and the RF designers measure the physical and radiation effects by using the Maxwell's equations. In addition to providing insights into the useful software enhancements, this series broadcasts the voices of different bloggers and experts about their knowledge and experience of various tools in the Virtuoso IC-Packaging world along with the nuances of RF, microwave, and high frequency designs. Watch out for our posts on Mondays.

Heterogeneous integration of components using different process technologies can appear to be magic! It mitigates the high cost of homogeneous system-on-chip (SOC) integration by allowing designers to combine proven designs, which use older nodes, on substrates by using newer process technologies. Traditional outsourced assembly and test (OSAT) vendors and IC vendors are competing to provide integration methodologies, such as Fan-Out Wafer-Level packaging, which can be used to build smaller and more efficient systems. Cadence is uniquely positioned to build and assemble ICs and interposers from a wide array of process technologies by taking advantage of proven capabilities in its as Allegro®, Virtuoso®, and AWR® platforms. Interoperability between the platforms is crucial to enable the seamless use of features from different tools. Technology, libraries, and design data must be interoperable to avoid the need for translators, which can increase the possibility of data being misinterpreted or missed during conversion.

But why do libraries have to be unified? And what does unification mean? Unification implies a single view of the data and a consistent representation of technology, libraries, and design data. The packaging ecosystem is evolving at Cadence. As new features become available on various platforms, consistent interpretation of the underlying data is crucial to provide the flexibility that users require. There are multiple platforms in the Cadence ecosystem that provide best-in-class features to enable the integration of components using different process technologies. For example, the SiP Layout Option offers a wide array of features that are used extensively in package design to assemble and implement packages, modules, and boards. AWR software products offer a rich set of RF module design features that can be used to design sensitive components, such as baluns and filters. Last but not least, the Virtuoso RF Solution offers the ability to assemble multiple technologies into a single cockpit to allow co-design, cross-technology path finding, and electromagnetic analysis. This calls for seamless interoperability between the various platforms.

Unification starts with technology and libraries and spans through schematics and layouts. Unified libraries provide a single point of entry for all Virtuoso driven multiple technology flows. The aim of library unification is consistent organization and interpretation of schematic symbols, and footprints, and component definition mapping between schematic symbol and footprints, TILP super masters, part definition CSV files, and simulation models. Importers are provided to create unified libraries from various sources, such as existing SiP Layout Option libraries and discrete part libraries from popular IP vendors. These libraries can be used for the implementation and verification of hierarchical schematics and layouts that span across boards, modules, packages, and ICs in an intelligent system design.

A unified interface implies a single-view representation of all the data and does not allow for tool-specific views to be stored in the central repository. This implies that padstacks and symbol/component definitions from the Allegro platform are converted into views in the unified library while adhering to a pre-defined data model. Note that it does not mean that the original padstack or symbol definition file is stored in the unified library—they are converted into technology-neutral footprints in the unified library. A footprint is interpreted through special OpenAccess Pcell called Technology Independent Layout Pcell (TILP) that understand how to interpret packaging concepts, such as die flipping, connecting to the top or bottom of the package substrate, die stacking, optical shrink, thermal shrink, and so on.

Design units and accuracy, layer cross-sections, process constraints, and via definitions are present in the technology database. In a multi-technology environment, it is important to defer the evaluation of technology-specific information, such as database units and layer binding. This allows the evaluation to occur at the point of instantiation rather than definition. When a component is instantiated in a design, the technology database of the design is consulted to rescale geometries and rebind layers to accommodate the host technology. This is a critical feature of unified libraries. When TILPs are instantiated in a design, users can set parameters on the schematic or layout instance to indicate where and how the component sits on the substrate. IC instances can be flipped to have the chip facing down and mirrored to connect to the bottom of the substrate. They can be embedded into the substrate to sit in cavities or stacked on top of one another to create a die stack. Optical and thermal shrink factors can be specified to adjust pin and boundary geometries. Packages can be placed in packages to create a hierarchical topology. All these parameters impact the resolution of layer names while evaluating TILPs. Information about discriminating parameters to identify part numbers and bill of materials (BOM) properties is stored to allow design variants. Schematic symbols that match the footprint are also stored in the unified library. Finally, the mapping information about the front-end and back-end names corresponding to schematic and layout views is also stored in a unified library.

To cut a long story short, when all the tools in the ecosystem consume unified libraries, you will be able to move seamlessly between tools depending on available features, designer comfort, and expertise. The freedom of building various flows that combine the best features from each tool lies with you!
For example:

A Virtuoso schematic-driven SiP Layout implementation flow followed by co-design and verification in the Virtuoso platform and ending with manufacturing and signoff in SiP Layout Option
A Virtuoso schematic-driven Virtuoso layout implementation and co-design/verification that ends with manufacturing and signoff in SiP Layout Option
A verification flow that allows the extraction of parts of an entire system that can be stitched into a schematic for simulation

This isn’t it; there is much more to tell. Stay tuned for more on this subject in the next few blogs.

Guru Rao and Deepti Mishra Gupta

About Virtuoso Meets Maxwell

Virtuoso Meets Maxwell series includes posts about the next-generation die, package, and board design flow with a focus on reinventing and optimizing the design process to ensure that the designer remains a designer! Keep watching!

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