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IC25.1
arc
INCAS
Virtuoso
CAS
Application Readiness Checker
Virtuoso Layout Suite
LVS Check
Incremental CAS
Connectivity Analyzer
IC23.1

Virtuoso Studio: Excellent XL- Layout XL Tools for Faster LVS Closure

16 Apr 2026 • 4 minute read

Our new AI-powered custom design solution, Virtuoso Studio, leverages our 30 years of industry knowledge and leadership, providing innovative features, reimagined infrastructure for unrivaled productivity, and new levels of integration that stretch beyond classic design boundaries. In this blog series, learn how the best analog design tools just got better to help you keep pace with your challenging design issues.

Just like a jigsaw puzzle is complete only when the assembled pieces accurately match the picture on the box, your layout design is complete when it matches the source schematic. The layout versus schematic (LVS) checks ensure that the final design matches the intended outcome and thatLVS Checks matching layout versus schematic correspondence is achieved.

Latest Layout XL Tools That Assist You in LVS Verification

We have introduced several tools in the Virtuoso Layout Suite that not only speed up your LVS checks but also help you achieve an LVS-issues-free design overall. You can use these tools in different ways, at different design stages, and check different aspects of the design.

Incremental Check Against Source: Always‑On Design Verification

Incremental Check Against Source enables continuous monitoring of layout updates in real time. Any interactive modification, such as copying shapes, editing properties, creating or deleting instances, triggers a check against the schematic. If the change causes a mismatch, the tool displays glyphs on the canvas and adds markers to the CAS tab of the Annotation Browser.

Incremental checks cover several categories of mismatches:

  • Unbound – Objects present in the layout but missing in the schematic
  • Ungenerated – Objects present in the schematic but missing in the layout
  • Master difference – Incorrect or unexpected master cell
  • Connectivity difference – Inconsistent connectivity between layout and schematic
  • Parameter difference – Mismatched device parameters

In the IC23.1 release, you can enable the feature by clicking the incas icon on the Options toolbar in the layout window. It is enabled by default in the IC25.1 release.

Once active, the tool provides instant feedback as you work, helping you catch errors early and maintain clean schematic‑layout correspondence.

Diagnosing Connectivity Issues with the Connectivity Analyzer

In the IC25.1 release, Virtuoso Layout EXL and above provide a connectivity‑aware design environment that automatically flags shorts, opens, and other connectivity‑related issues as connectivity markers. These markers appear directly on the layout canvas and are also listed in the Annotation Browser, making it easy to spot when something in the layout doesn’t align with the intended connectivity.

Although the markers can make issues very easy to spot, the default marker descriptions can sometimes feel generic, leaving it unclear why the violation was flagged or whether it represents a genuine issue or an intentional design choice.

To help you quickly interpret and act on these markers, Annotation Browser offers the Analyze option. With a simple right‑click or by clicking the hyperlinked Analyze text in the description, you can run Connectivity Analyzer. This tool provides deeper insights into the reported violations and can automatically apply fixes or add overrides where appropriate, making it far easier to resolve connectivity mismatches with confidence.

Application Readiness Checker: Your LVS Safety Net

The Application Readiness Checker streamlines how the layout is checked and updated against the schematic. It provides a clear, one‑to‑one mapping between each check and its corresponding update, so you always know exactly what was verified and what can be updated. You can choose which checks to run depending on your application needs, making the process flexible and focused.

The checker is also extensible. You can register your own SKILL‑based check and update tests.

The checks generate markers that appear on the CAS tab of Annotation Browser, and all marker messages automatically flow into the final Application Readiness Checker report.

In Virtuoso Layout XL or higher tiers, you can launch Application Readiness Checker by selecting Check and Update on the Connectivity menu or Application Readiness Checker on the Verify menu.

LVS checks are no longer a bottleneck. With continuous verification, clear diagnostics, and targeted fixes, the latest Layout XL tools help you catch mismatches early, stay aligned with the schematic, and reach LVS closure faster—with fewer surprises at signoff.

Related Resources

 Product Manual

Virtuoso Layout Suite XL: Connectivity Driven Editing User Guide

  • Design Check Using Application Readiness Checker
  • Incremental Check Against Source
  • Connectivity Analyzer
  Training Bytes (Videos)

Application Readiness Checker

Incremental Check Against Source

  Rapid Adoption Kits

Application Readiness Checker

Virtuoso Layout Connectivity Analyzer

  Blogs

Virtuoso Studio: Excellent XL - Next-Gen Layouts with Virtuoso Layout XL

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For more information on Cadence circuit design products and services, visit www.cadence.com.

Happy Reading!

Sucharita Mehta


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