The new release of the Virtuoso platform (ICADVM18.1) offers groundbreaking analysis capabilities and an innovational new simulation-driven layout for more robust and efficient design implementation as well as extending our support for the most advanced process technologies. With this solution, we are able to significantly improve productivity through advanced methodologies and provide the most comprehensive set of solutions in the industry with an interoperable flow across chip, package, module and board.

With each new technology node, routing becomes even more challenging. The number of design rules has increased significantly - as have the number of metal layers. Designs are becoming far more complex and require advanced constraints to drive the implementation of Analog and Mixed signal flow. To overcome some of these challenges, designers require quick and accurate modeling of congestion for floorplanning, pin optimization, and die size reduction.

In this blog, we introduce you to the new Congestion Analysis assistant and how it helps users to visualize, analyze, and plan nets in the design.

Introducing Congestion Analysis Assistant

The new Congestion Analysis assistant lets the users extract, display, and analyze routing congestion both visually and statistically. Furthermore, the assistant gives the designer tools to optimize routing paths for critical nets and net groups. Here are a few reasons why you should try out the new Congestion Analysis assistant.

Easy to Visualize Routing Congestion

• Heatmap
• Histogram
• Statistics

The Heatmap graphically displays congestion hot spots in the layout window. This form of display is not new in EDA. However, in large or complex designs, Heatmap might hide important information by itself. To complement the Heatmap, we are introducing the first ever "Congestion Histogram". It shows congestion in a novel yet easy to understand display that can be customized and filtered. In addition, we have made actual routing statistics available to aid you in the interpretation of the congestion results.

Easy to Analyze Routing Congestion

• Congestion based filterable heatmap
• Customizable histogram
• Net probing and path display

With large, complex designs, it can be hard to disseminate important information quickly and efficiently. For this reason, we have incorporated many ways to quickly dive down and focus on congested areas of interest. We’ve made it possible for the users to filter congestion data in various ways, customize the Histogram’s “congestion buckets”, and display the reduced data set onto the Heatmap. You can cross probe critical nets in the Navigator Assistant and see them displayed over the Heatmap.

Easy to Plan and Optimize

• Global bias constraints
• Automated pin optimization
• Integrated floorplanning with Design Planner

It is good to find out that a design has over congested areas. However, how can you resolve it and trust that the design will converge?

For this, we are introducing a new method to graphically plan nets and net groups in the design. This is a unique route planning feature that relies on a new type of constraint called "Global Bias". The Global Bias constraints allow the user to set preferred routing paths and areas in the design for routing a specified net or net group – think of it like planning a driving route on your favorite map application.

Using this exclusive set of routing features along with the newly introduced Design Planner in ICADVM 18.1, users can now experiment with multiple floorplans and see how different placement strategies impact routing convergence. This can enable users to drive a tighter design and a smaller die size.  It also gives the confidence that the design will converge while considering all routing constraints and requirements.

Keep calm and Happy routing! 

Watch out for our upcoming Virtuoso platform ICADVM 18.1 release, and then take a fresh new look at the new Congestion Analysis assistant. 

Related Resources

• Congestion Analysis and Global Biasing
• Virtuoso: The Next Overture - Introducing Design Planner

For more information on Cadence circuit design products and services, visit www.cadence.com.

Contact Us

For more information on the New Virtuoso Design Platform, or if you have any questions or feedback on the features covered in this blog, please contact  team_virtuoso@cadence.com.

To receive similar updates about new and exciting capabilities being built into Virtuoso for our upcoming Advanced Nodes and Advanced Methodologies releases, type your email ID in the Subscriptions field at the top of the page and click SUBSCRIBE NOW.

Parul Agarwal, Michael Hunter, and Mark Rossman (Team Virtuoso)