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Featured

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Virtuoso Studio IC23.1 ISR15 Now Available

Virtuoso Studio IC23.1 ISR15 production release is now available for download.

Virtuoso Release Team
• 2 min read
featured , Virtuoso Studio , IC Release , IC Release Blog Announcement , Virtuoso

Virtuoso Studio IC25.1 Now Available

Virtuoso Studio IC25.1 production release is now available for download.

Virtuoso Release Team
• 17 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement
Analog/Custom Design

Latest blogs

Virtuosity: A Very Large Number of Things I Learned in September and October 2014…

There has been a flurry of activity on COS over that past couple of months. I can…

• 8 min read
AMS , MMSIM , Advanced Node , ADE XL , Virtuoso , Analog Design Environment , Custom IC Design , Virtuoso Layout Suite XL , IC 6.1.6

The Elephant in the Room: Mixed-Signal Models

Key Findings: Nearly 100% of SoCs are mixed-signal to some extent. Every one of these…

• 5 min read
metrics-driven methodology , real number modeling , uvm , CPF , RNM , UPF , mixed signal , MDV , verification

It’s Late, But the Party is Just Getting Started

Key Findings: Many more chip programs are crossing the tipping point and need advanced…

• 6 min read
AMS , analog behavior , AMS-Designer , AMS Designer , analog behavioral models , analog/mixed-signal , AMS Verification

Virtuosity: 20 Things I Learned in July and August 2014 by Browsing Cadence Online…

Apologies for skipping a month, but things got a bit hectic, so enjoy a double-dose…

• 3 min read
EAD , AMS , Rapid Adoption Kit , ADE XL , Virtuoso Analog Design Environment , Monte Carlo , Layout , Virtuoso , Virtuosity , statistical corners , Virtuoso Layout Suite , IC 6.1.6

EDA Plus Academia: A Perfect Game, Set and Match

Excuse the tennis analogy, but just coming out of Wimbledon! However, EDA and academia…

• 2 min read
DAC , Carnegie Mellon University , EDA , memory circuit yield , Semiconductor , university program

Virtuosity: 21 Things I Learned in May and June 2014 by Browsing Cadence Online …

Application Notes 1. Setting PVS to QRC av_extracted Flow with tsmc28 (& tsmc40…

• 4 min read
Variability Aware Design , ADE GXL , VSR , Routing , ADE XL , Layout , Spectre , Analog Design Environment , Placement , Virtuoso Layout Suite XL , IC 6.1.6

Virtuosity: 19 Things I Learned in April 2014 by Browsing Cadence Online Support

Plenty to keep you busy this month. Lots of RAKs, videos, and new Quick Start Guides…

• 4 min read
Variability Aware Design , AMS , Virtuoso online support , Routing , ADE XL , Virtuoso Analog Design Environment , Spectre , Schematic Editor , Virtuosity , Virtuoso Layout Suite XL

High Yield Analysis and Optimization - How to Design the Circuit to Six Sigma

Why high yield analysis? One failed memory cell out of millions cells will cause…

• 2 min read
Six Sigma , Virtuoso , Circuit Design , analog design , high yield analysis

How Can You Learn About Mixed-Signal Verification and Implementation Flows at Your…

The vast majority of SoCs today are advanced mixed-signal designs. The old mixed…

• 3 min read
real number modeling , AMS Designer , EDA training , SV-RNM , DMS , mixed signal , Schematic Model Generator , RAKs

What’s New in Virtuoso ADE XL in IC616 ISR6?

In a previous post, I explained the release model used for Virtuoso ADE and ViVA…

• 1 min read
Analog Design Environment , custom IC simulation , ADE XL , Virtuoso Analog Design Environment , Virtuoso , ADE-XL , Circuit Design , Custom IC Design , IC 6.1.6

Keeping Your Circuit in Tune: Sensitivity Analysis and Circuit Optimization

Anyone who has ever played a musical instrument knows how hard it can be to keep…

• 4 min read
Variability Aware Design , ADE GXL , worst case corners , optimization , Virtuoso , statistical corners , Variation

Virtuosity: 15 Things I Learned in March 2014 by Browsing Cadence Online Support

Highlights for this month include lots of useful Physical Verification System (PVS…

• 2 min read
Variability Aware Design , ADE GXL , Virtuoso , Analog Design Environment , PVS

What's New(-ish) in ADE XL in IC 616 ISR 3?

Development Model for ADE and ViVA Virtuoso Analog Design Environment (ADE) and…

• 1 min read
Analog Design Environment , ADE XL , Custom IC Design , IC 6.1.6

Mismatch Contribution Analysis in Virtuoso Analog Design Environment GXL

When Monte Carlo analysis shows device mismatch variation has become problematic…

• 2 min read
ADE GXL , ADE XL , mismatch variation , Virtuoso Analog Design Environment , Monte Carlo , mismatch contribution analysis

Efficient Design Migration Using Virtuoso Analog Design Environment GXL

Requirements for decreased time to market, reduced silicon area, and minimized power…

• 2 min read
Analog Design Environment , ADE GXL , ADE XL , Virtuoso , Custom IC Design , Design Migration

Fast Yield Analysis and Statistical Corners

The Virtuoso Analog Design Environment XL Monte Carlo sampling methods are Random…

• 3 min read
ADE GXL , ADE XL , fast yield analysis , Virtuoso Analog Design Environment , Monte Carlo , statistical corners

Virtuosity: 14 Things I Learned in January and February 2014 by Browsing Cadence…

Time just got away from me last month, so here's two months worth of new content…

• 2 min read
AMS , Corners , ADE , ADE-GXL , PVT corners , Custom IC Design , Virtuoso Layout Suite

What's the Worst that Could Happen?: Worst-Case Corners in ADE GXL

In addition to combinations of temperature range and power supply voltages (usually…

• 2 min read
Variability Aware Design , Corners analysis , worst case corners , Virtuoso Analog Design Environment , ADE-GXL , Analog Design Environment

What Your Circuit Doesn't Know, Can Kill It!

Device variation has been a long-standing problem in custom design. Over the years…

• 1 min read
IP , post-extraction , corner , in-design , Virtuoso Analog Design Environment , physical implementation , device variation , IC design

Virtuosity: 15 Things I Learned in December 2013 by Browsing Cadence Online Supp…

With this month's title, I'll need to start adding the year, as this marks the one…

• 3 min read
RF Simulation , AMS , Low Power , PCells , ADE , Layout , Virtuoso , Spectre , Analog Design Environment , ADE-XL , PVS , SKILL

Virtuosity: 12 Things I Learned in November by Browsing Cadence Online Support

New content on a wide variety of topics in November. Product Information 1. Cadence…

• 2 min read
EAD , AMS Designer , Virtuoso , AMS simulation , PVS

Support for Low Power Mixed Signal Designs in Virtuoso Schematic-XL

Why is There a Need for Low Power Solutions? With an increase in the demand for…

• 8 min read
Low Power , mixed signal design , mixed-signal methodology , mixed signal solution , CPF , LVS , cdl , Schematics-XL , Mixed-Signal , analog/mixed-signal , Virtuoso , mixed signal

SKILL for the Skilled: SKILL++ hi App Forms

One way to learn how to use the SKILL++ Object System is by extending an application…

• 10 min read
layout hierarchy , Jim Newton , schematic hierarchy , object orientation , Layout , Virtuoso , object system , software development , design hierarchy , SKILL++ , SKILL , Schematic

SKILL for the Skilled: Simple Testing Macros

In this post I want to look at an easy way to write simple self-testing code. This…

• 5 min read
Team SKILL , programming , shuffle , Jim Newton , SKILL for the Skilled , macros , Lisp , SKILL++ , SKILL

Virtuosity: 12 Things I Learned in October by Browsing Cadence Online Support

Lots of routing, a little AMS, and finishing off with some fun... Application Notes…

• 3 min read
SystemVerilog , AMS , PAD , Virtuoso Space-based Router , VSR , Routing , Spectre , mixed signal

IC6.1.6 Virtuoso Space-Based Mixed-Signal Router (VSR)

Virtuoso Space-Based Router (VSR) is routing solution integrated into the Virtuoso…

• 4 min read
Technology on tour , MS ToT , VSR , mixed-signal ToT , mixed-signal training , Router , tech on tour , Open Access , analog/mixed-signal , OA: OpenAccess , tech-on-tour

Virtuosity: 16 Things I Learned in September by Browsing Cadence Online Support

Rapid Adoption Kits By now, I think you know what RAKs are, and that they include…

• 3 min read
custom/analog , Routing , Rapid Adoption Kit , pin placement , Virtuoso Analog Design Environment , Layout , Virtuoso , Analog Design Environment , Schematic Editor , ADE-XL , Virtuosity , Custom IC Design , Virtuoso Layout Suite , VLS XL , Virtuoso Layout Suite XL

SKILL for the Skilled: How to Shuffle a List

The previous post of SKILL for the Skilled presented some ways to systematically…

• 5 min read
Team SKILL , programming , shuffle , Jim Newton , IC615 , SKILL for the Skilled , permutations , random , Lisp , SKILL++ , SKILL
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