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Physical design challenges such as congestion, routing, on-chip variation (OCV), and unconstrained paths are significant issues in achieving the design goals. Managing the routing congestion and physical design challenges with the least amount of effort is a big problem for physical design engineers. Further, the usage of advanced nodes and increasing functionality over SoC is leading to rising complexity and conflicting PPA and TAT goals.
Cadence support and rapid adoption kits (RAKs) enable our partners to achieve the best results and resolve such challenges quickly with the least effort. All such efficient practices with advanced solutions to handle the physical design challenges are available at the Cadence Support portal site. It has collated years of experience with experts to supply tips and techniques to help meet your design PPA and TAT requirements. This resource is available 24X7.
This blog talks about mitigating these physical design challenges using Cadence support.
With the adoption of advanced nodes and industry inclination towards reducing metal layers available for routing, congestion is increasing and is a bottleneck in meeting PPA and TAT goals. Analyzing congestion at an early stage will aid in a quicker design closure even though it appears at the routing stage of the design.
Congestion may result due to:
It is very important to consider the congestion, which can be reduced using the options below:
Track opt-based routing makes faster design closure possible, which reduces the duration gap between pre-route and post-route. You may find more details and recommendations for resolving the congestion in the RAK.
As digital design challenges grow with each process node shrinking, new placement, routing, and clocking capabilities are needed to meet PPA and TAT goals. One of the main CTS goals is to achieve minimum clock tree area/power.
Although the schemes such as mesh and conventional H-tree result in a higher quality of results (QoR) than normal CTS, they suffer from a low degree of freedom in a clock tree design, man-hours for creation, and high-power consumption. Traditional schemes that use skew slack, minimization, and performing CTS suffer from a timing gap between ideal pre-CTS and propagated clocks post-CTS. Please refer to clock tree synthesis debugging techniques to learn more about CTS.
Finding the ideal balance between avoiding blockages and power rails,
adhering to partition, module, and power domain limits, and optimizing insertion delay, power, and skew is made easier with the help of Cadence, flexible - H.
The integration of CTS and physical optimization is made possible by clock concurrent optimization (CCOpt). The Early Global Route (eGR), which also delivers further improvements in total negative slack (TNS) and worst negative slack (WNS), as well as predictable design closure, is a feature of the Innovus Implementation system. CCOpt with Innovus offers the below advantages with an excellent CTS:
The nominal delays of all instances have traditionally been scaled with a single derating factor, in OCV, to simulate the on-chip process variation. This may result in over-optimism or pessimism, excessive design, and a longer turnaround time for timing closure. The logic timing is impacted by the timing changes caused by (OCV). These variances could cause ICs from one batch of wafers to perform "quick" or "slow" in comparison to nominal estimates. If a design successfully completes both the slow corner and fast corner timing analyses, it is said to have complied with the time constraints. By addressing these obstacles, statistical OCV (SOCV) offers a fair balance between run time and accuracy for modeling variance. For each instance in the design, SOCV calculates the effect of local process variations on the delay and slew at a specific global variation corner. RAK SOCV debugging offers several ways to fix problems and debug on-chip variation. The SOCV debugging RAK provides various solutions to issues and debugging on-chip variation (OCV). It helps in faster debugging of SOCV-related issues, including investigating various timing analysis problems, reporting SOCV timing results, performing SOCV timing calculations, etc.
During static timing analysis (STA), designers often come across timing paths that are not analyzed by the STA tool. These paths can be intended to be analyzed, but due to constraint, setup, library, etc., issues may result in the path not being reported as a constraint timing path. All paths and ports should be constrained for ideal placements and the finest-suited outcomes. The uncontrolled paths that arise from setup, library, setup constraints, and other factors make it difficult to achieve the best placement and routing outcomes. Unconstrained path debugging RAK includes a thorough manual and a lab that goes over a variety of scenarios in which a path won't be reported as a constrained path. This article also includes a flowchart that illustrates the debugging strategy to be used based on the observations made at each stage to determine why the path isn't reported as a limited path.
When it comes to meeting timing constraints, Cadence's Tempus solution takes on the most complex problems, including complete signal integrity and others. It provides a solution to the unjustified pessimism brought on by on-chip fluctuation. It is capable of handling the ultra-low voltage effects at 7nm and below, which leads to statistical variance.
Cadence assistance and RAKs make use of the finest plans to overcome the physical design challenges and assist partners in achieving design objectives with less time and effort. The early analysis would permit a quicker design closure. Different flow adjustments made by designers aid in design convergence while achieving PPA objectives. Different flow adjustments aid in design convergence while achieving PPA objectives. More users utilize SOCV analysis as we advance to smaller geometry nodes to combat pessimism. The SOCV debugging RAK offers users a range of SOCV-related issues, fixes, and debugging techniques.