Voltus^TM IC Power Integrity Solution is a power integrity and analysis signoff solution that is integrated with the full suite of design implementation and signoff tools of Cadence to deliver the industry’s fastest design closure flow. The aim of this blog series is to broadcast the voices of different experts on how design engineers can effectively use the diverse Voltus technologies to achieve high-performance, accuracy, and capacity for next-gen chip designs.

The CMOS fin field-effect transistor (FinFET) process has been a breakthrough technology in the IC design space owing to low power consumption and better performance. Every new technology comes with its own set of challenges, and modern FinFET transistors are no exception. In FinFETs, circuit performance and drive strength have improved significantly, but these come at the cost of increased temperatures and heat dissipation. This heat generated in the transistor channel arises from the vertical current direction and high-power density. The vertical fins are surrounded by dielectric and have a very narrow channel to the substrate, thus providing poor pathways for heat dissipation resulting in localized self-heating. The increased temperature from self-heating can worsen electromigration and IR drop issues. The risk of such self-heating effects in FinFETs makes it mandatory to include them in device modeling and circuit simulation processes. In lower technologies, especially at 5nm and below, thermal analysis is inevitable. Design engineers need an accurate rather than a pessimistic analysis, given the minute fix margin. The conventional FinFET compact models used for accounting self-heating effects during simulation are unsuitable due to their high costs and growing circuit size.

This is where the Self-Heat Effect (SHE) analysis flow from Cadence^® Voltus^TM IC Power Integrity Solution comes to your rescue. It analyzes the reliability issues in FinFETs by reporting the increase in temperature (deltaT) for all the metal layers and instances in the design.  

In Voltus, SHE analysis is driven by front-end-of-line (FEOL) self-heat, back-end-of-line (BEOL) self-heat and their thermal coupling.

The following are some of the key capabilities of the Voltus SHE flow:

• Analyze the impact of self-heat on the power and signal electromigration reliability targets at high frequency and low voltage design nodes.
• Perform both Joule Heat (device heat due to signal RMS current) and Self-Heat (considers fin device heat and signal wire thermal heat) analyses at the full-chip level.
• Run the analysis at an early stage of the design and at signoff.
• Provide a detailed view of the temperature variations within the design.
• Display the high temperature regions.

Voltus SHE methodology facilitates an accurate reliability analysis in the FinFET technologies, enabling design engineers to seamlessly meet the stringent rules associated with the signal and power electromigration analyses.

Want to know more? To get a detailed and complete understanding of this flow, you can view the Signal Electromigration and Self Heat Analysis in Voltus video available on Cadence Online Support.

-Sakshi Nema

Related Resources

• Voltus IC Power Integrity Solution
• Voltus IC Power Integrity Solution User Guide

For more information on Cadence digital design and signoff products and services, visit www.cadence.com.

About Voltus Voice

“Voltus Voice” showcases our product capabilities and features, and how they empower engineers to meet time-to-market goals for the complex, advanced-node SoCs that are designed for next-gen smart devices. In this monthly blog series, we also share important news, developments, and updates from the Voltus space.

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