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Reliability has always been a concern for semiconductor devices used in various applications like medical, automotive, home appliances, etc. High-reliability devices demand functional safety and component reliability over long operational lifetimes. Hence doing an early stage reliability sign-off has become an important step in design to figure out how the devices behave in stressful conditions after a certain age or time.
To ensure high reliability, designers require accurate analysis of device performance over time without relying on pessimistic margining techniques that negatively impact PPA. To overcome the aging challenges in ICs, Cadence offers its latest breakthrough technology, which is Aging Aware Static Timing Analysis and Optimization, leveraging a unified flow spanning from Liberate characterization through Tempus STA and Tempus ECO, which enables designers to accurately analyze aging effects in the context of their design. This improved accuracy, in turn, allows for a re-examination of margins and subsequent PPA savings up to 10%.
Device Performance Degradation
There are two principal device degradation aging mechanisms designers need to analyze, in terms of the potential performance impact – i.e., Hot Carrier Injection (HCI) and Bias Temperature Instability (BTI). They result in changes in device drive currents and threshold voltages, but not an immediate failure of the circuit to operate. They relate to the presence of carrier “trap states” at the channel interface and in the gate dielectric stack. The result is a change in the effective electric field at the channel from an applied gate voltage.
Aging Aware Timing Analysis Approaches
Traditional Aging-based static timing techniques rely on derate methodology. In this method, the cycle time used during design timing closure would be multiplied by a conservative aging factor and released with the reduced frequency spec – i.e., a “guardband” approach. This method suffers from inaccuracy and pessimism and is often expensive to characterize. Such an approach ultimately leads to over margining, which can degrade the PPA by 10%, or it can fail to account for aging optimism scenarios which can lead to silicon failure.
Breakthrough Cadence Aging flow
The Cadence advanced aging solution consists of the characterization of stress condition-independent cell libraries that are used by the Tempus aging-aware STA and deliver aging-aware timing and optimization for digital designs. Unlike global derating or corner-based aging characterization, this advanced aging solution relies on the Liberate Trio suite, wherein they use Spectre to generate an aged netlist and feed this aged netlist to Liberate to generate an aged library for a specific duty cycle and arbitrary target usage profiles (segments of supply voltage, temperature, and age).
If you find the post useful and want to delve deeper into technical details, do watch these short training byte videos on Aging and Tempus Aging-Aware STA analysis present at Cadence Support.
Tempus Aging Aware STA with Liberate and Spectre (Video) (cadence.com)
Tempus User Guide
Tempus What's New (22.10)
Tempus Text Command Reference (22.10)
Tempus: Design Robustness - Breakfast Bytes - Cadence Blogs - Cadence Community
Advanced Aging | Cadence
Liberate Trio Characterization Suite | Cadence
For more information on Tempus and Cadence digital design and sign-off products and services, visit Tempus Timing Signoff Solution | Cadence.
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