Enabling End-to-End EDA Flow on Arm-Based Compute for Infrastructure Flexibility

The world's insatiable demand for compute will only continue to increase with the proliferation of AI. As compute demands grow, on-premises chip design becomes more complicated and costly, challenging existing infrastructure due to increased systems-on-chip (SoC) complexity, shorter time to market, and the need for energy efficiency and better performance per dollar per watt. In support of designers' need for scalable compute while working on applications such as agentic AI, Cadence and Arm have expanded their long-standing partnership to deliver a comprehensive, end-to-end EDA flow on Arm-powered infrastructure.

To accelerate Arm-based SoC design, Cadence has made its digital design and implementation capabilities available on Arm-optimized cloud environments, complementing its existing verification tools. This broadened collaboration builds on existing Arm Neoverse verification support and now brings Cadence's full suite of EDA solutions – including the Innovus Implementation System, Genus Synthesis Solution, Tempus Timing Solution, and Pegasus Physical Verification System—natively to cloud platforms built on Arm.

"Cadence's expansion of its EDA portfolio on Arm Neoverse unlocks new levels of efficiency and scale for designers tackling increasingly complex, AI-driven workloads," said Dermot O'Driscoll, VP Products and Solutions, Cloud AI Business Unit, Arm. "By pairing Arm's performance-per-watt leadership with Cadence's end-to-end design and verification capabilities, we're enabling customers to rapidly design intricate next-generation silicon for applications from cloud to edge faster and more efficiently than previously possible."

"To meet today's needs and tomorrow's innovations, Cadence and Arm have extended their collaboration to bring Cadence digital design and implementation tools to the Arm Neoverse® compute platform," said Yufeng Luo, corporate vice president of research and development at Cadence. "This expands on the existing Arm Neoverse verification solutions, enabling designers to select the best compute platform for their chip design requirements."

Understanding EDA On Arm-Based Compute

EDA on Arm-based compute involves deploying advanced EDA solutions on scalable cloud platforms, enabling engineers to develop complex SoCs efficiently. This approach leverages high-performance cloud infrastructure to run computationally intensive design workflows that traditionally relied on on-premises data centers. As the demand for compute-heavy workloads increases—driven by AI, 5G, and hyperscale data centers—traditional infrastructure often struggles to keep pace. Cloud-native architectures provide design teams with unlimited compute capacity, ensuring the precision and reliability necessary for modern chip verification and development. This strategy addresses key industry challenges, including rising design complexity and the need for rapid iterations.

Arm's Neoverse CPU architecture, specifically designed for data center workloads, offers a scalable, energy-efficient alternative. All of the leading hyperscalers have already embraced Arm-based infrastructure, signaling a shift in industry dominance.

Arm Neoverse CSS: The Backbone of Cloud Innovation

Arm Neoverse Compute Subsystem (CSS) provides the high-performance, scalable compute foundation needed to support modern EDA workloads in the cloud. By offering validated silicon and a robust infrastructure platform, Neoverse CSS enables partners to focus on building differentiated solutions rather than underlying system integration.

With this foundation in place, Cadence has optimized its EDA flows for seamless deployment on Neoverse-based platforms. Together, Cadence and Arm are lowering the barrier to designing Arm-based custom solutions and ensuring customers have an efficient, cloud-ready path to developing next-generation SoCs.

Why Cadence Is Enabling Full EDA Flow on Arm-Based Compute

Looking ahead, the implications of this collaboration extend far beyond technical enablement. As agentic AI evolves into systems capable of autonomous planning, decision making, and executing complex workflows at scale, the demand for highly efficient, scalable, and versatile compute infrastructure has never been greater. The scalability of cloud infrastructure allows design teams to access virtually unlimited compute resources during peak demand periods while scaling down during idle times. This elasticity is particularly valuable for EDA workloads that exhibit highly variable computational requirements throughout the design cycle. By enabling EDA in the cloud, powered by Arm compute, Cadence is helping customers:

• Meet the scalable compute demands of agentic AI applications
• Accelerate time to market for complex chips, including Arm-based SoCs
• Reduce infrastructure costs and energy consumption
• Scale design workflows elastically across cloud environments
• Achieve first-pass silicon success with optimized flows

This collaboration also supports Cadence's Intelligent System Design strategy, integrating AI and cloud-native capabilities to meet the evolving needs of semiconductor innovation.

Final Thoughts

As the industry continues to evolve toward more complex, heterogeneous designs, the scalability and efficiency of cloud-based EDA tools will become increasingly critical to maintaining a competitive advantage. The availability of Cadence front-end to tape-out flows on Arm-based cloud eliminates traditional barriers to advanced chip design while providing access to cutting-edge AI-driven optimization capabilities. The strategic partnership between Cadence and Arm in cloud EDA deployment represents a transformative opportunity for the semiconductor industry.

Read More

• Cadence and Arm Are Building the Future of Infrastructure
• Arm-Based SoC Design – Develop Optimized Arm SoCs More Efficiently
• Arm's Cloud EDA Success: Two Paths to Greater Value
• Cadence in Collaboration with Arm Ensures the Software Just Works
• Benchmarking Cadence Tools on Arm-Based Servers in the Cloud
• Arm Applies Cadence Cerebrus to Optimize PPA of Next-Gen 3nm Core Implementation

Explore more at the Software Ecosystem Dashboard for Arm and Arm-based solutions at Cadence.