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The increase in compute and data-intensive applications and the need for lower power consumption have resulted in a rapidly growing number of Arm-based devices in various market segments; this requires fast time to market (TTM) and support for off-the-shelf generic Oss.
Arm SystemReady is a compliance program that ensures systems are designed to specific standards, enabling software to “just work.” Checking for compliance can be costly, as historically, it demands a UEFI or Linux boot that runs very slowly on RTL. To catch issues earlier, when they are easier and less expensive to debug and fix, Cadence, in collaboration with Arm, has developed a solution for pre-silicon compliance testing for Arm-based designs. This solution helps to accelerate the pre-silicon phase and reduce the risk of re-spins. Demonstrating a pre-tapeout OS boot can be an essential test for building confidence in the design. This blog introduces the Arm SystemReady program and discusses how Cadence’s collaboration with Arm helps check the pre-silicon Arm SystemReady architecture compliance tests to be run on bare-metal (BM) RTL.
The Arm SystemReady compliance certification program provides the solution for different market segments. The program is based on industry standards and contains a compliance test suite and a process for certification. Ensuring SystemReady compliance is challenging and an additional workload in large SoC validation. Arm and Cadence announced their collaboration on SystemReady pre-silicon solution for booting a generic off-the-shelf operating system (OS) on any SoC. It is a significant milestone and requires the SoC to meet minimum hardware and firmware standards. Arm SystemReady pre-silicon compliance testing can test chips before tapeout to avoid costly reworks and reduce the risk for our silicon partners.
Arm SystemReady is a program established by Arm to ensure out-of-the-box compatibility for OSes. It is a compliance certification program based on a set of hardware and firmware standards. It enables operating systems to work in such a way so that SystemReady-certified devices have a base level of interoperability while encouraging innovation and differentiation across a broad set of devices ranging from servers and hyperscalers to embedded IoT and cloud edge-based devices.
The compliance certification program tests and certifies that systems meet the SystemReady standards. It ensures that operating systems and subsequent software layers will work seamlessly.
The SystemReady program is a set of crucial specifications consisting of Base System Architecture (BSA) and its market-specific supplements like the Server Base System Architecture (SBSA), and Base Boot Requirements (BBR) specifications, plus a selection of supplements.
SystemReady consists of a set of bands with specifications available to suit the different market segments. Initially, these new specifications support four prominent bands of SystemReady, plus a Security option.
To learn more please visit Arm SystemReady page
PCIe compliance is an essential component because it directly delivers or underlies the primary I/O for many server interface protocols for fast storage, fast networking, and off-die coherent interfaces. As one of their key features, server-class SoCs have a common interface to PCIe devices. There are certain interoperability issues when integrating Arm with PCIe, including:
Cadence has been working with Arm for a couple of years to reduce the tests to a minimal bare-metal test suite with a PCIe traffic generation library that will emulate faster than the UEFI test suite for a quick turnaround hardware debug.
BSA/SBSA compliant silicon ensures that the operating system works before tapeoutEach chip's spin (production run) is a very costly endeavor for silicon SoC manufacturers. If that physical product is not compliant with the Base System Architecture (BSA) specification requirements, it leaves the manufacturer having to employ costly software workarounds. Or, in the worst case, re-spin the product. To simplify and better ensure system compatibility for SoC designers and integrators, Arm developed the pre-silicon BSA/SBSA compliance tests, which define a set of checks that integrators must pass to meet this goal. The Cadence-Arm collaboration brings tremendous benefits to partners by providing a pre-silicon compliance solution.
Typical SoC design starts with architecture exploration, IP selection, design, and verification, leading to tapeout. Once silicon is available, some further bring-up exercises are conducted. In order to be SystemReady, SoC must implement the BSA/SBSA specifications, and then, during verification, test for pre-silicon BSA/SBSA compliance. Compliance testing is not a substitute for design verification, but rather complements it—compliance testing focuses on the system-level and software visible behavior defined by the architecture specification, rather than microarchitecture implementation correctness.
Arm collaborated with Cadence for a pre-silicon compliance solution that integrates tests (ACS), drivers, and exercisers for an out-of-the-box experience.
Traditionally, silicon compliance testing/ certification is done post-silicon, which is too late to fix the hardware issues found. Cadence enables checking the system architecture rules for servers much earlier in the design cycle. Using this solution, you can run the Arm compliance test using bare-metal (BM) software, as your SoC RTL is getting ready while working on the hardware emulator (such as Palladium). The pre-silicon tests can also be run on UEFI, in addition to bare metal. UEFI enables running the tests with minimal porting effort.
Further, Cadence brings this unique solution with a controllable PCIe endpoint to ease out the verification on top of Linux, which is very difficult to do post-silicon, and offers the following advantages:
Therefore, in collaboration with Arm, we built a solution to check pre-silicon compliance much earlier in the cycle, with the confidence that once your SoC goes out into silicon and you bring up the OS, you wouldn't need to add costly patches and delays. An approach using Cadence System verification IP enables engineers to get a system-level test suite up and running within half a day that can validate PCIe integration against SystemReady requirements. This methodology can also be used to demonstrate booting SUSE Linux and Windows from a flash memory device model connected to PCIe, which is creating significant interest in the advanced server community.
SystemReady standards ensure that Arm-based servers, infrastructure edge, and embedded IoT systems are designed to specific requirements, enabling generic off-the-shelf operating systems. The underpinning of this program is the hardware and firmware specifications that allow the common OS to boot on Arm devices. Cadence, in collaboration with Arm, has designed a solution that allows partners/customers to do pre-silicon compliance checks much earlier and feel confident about the OS booting up without costly patches and delays and offers the following benefits:
This approach enables engineers to get a system-level test suite up and running within half a day to validate PCIe integration against SystemReady requirements.