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Moinak Gorai
Moinak Gorai

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CCSN characterization
CCSN
Liberty Variation Format
Reference-based modeling
cross coupled capacitance
characterization
composite current source noise
noise in digital circuit
CCS Noise
Library Characterization Tidbit
channel connected blocks
coupling cap
Liberate
noise propagation
Liberate Characterization Portfolio
Stage-based modeling
CCB
timing

Library Characterization Tidbits: Importance of Noise Analysis and the Role that Liberate Plays

4 Mar 2021 • 5 minute read

Library Characterization Tidbits

Hello everyone,

A few days back, I was looking out of my office window. The streets were busy again with the same old traffic jams, crowded roads, and honking vehicles. All symptoms of the life gaining normalcy after the lockdown norms easing gradually!

So, do only the crowded streets have noise? Well no, even the electronic circuits have noise. If you are wondering how "noise" comes into chips and SOCs, and how engineers deal with them, then continue reading this blog because you might find answers to some of your questions.

The hustle bustle of the cities is only an example of the external noise, which we are aware of through the obvious observations of our sensory organs. However, in terms of electronics, a noise maybe defined as any kind of unwanted signal that interferes with the real signal in a timing path in a cell or circuit. To understand why analysis of noise is important in the circuits and how Cadence® LiberateTM Characterization Portfolio can help, let us now explore some questions that people have about noise characterization.

Why noise characterization is important from a designer’s perspective?

While designing a circuit, the main intent of a designer is to ensure that the device is functional for a wide range of operating conditions. If a noise is injected in the circuit, then it might malfunction completely if the noise is not analyzed properly. In most cases, coupling capacitance causes electrical pulses that are the main form of noise inside a circuit.

Today, in the latest technology nodes, we want our devices to be as small as possible, but without compromising the features. This asks for more transistors in the same chip area, which means more and more smaller transistors are sitting closely. Also, the wires and interconnects connecting those transistors in such close proximity gives rise to coupling capacitance more than ever.

Now you may ask that how does this lead to more noise in the circuit? Well, let’s understand it better through the figures below. In the diagram shown below, when the aggressor net switches, it makes the victim net to switch due to cross coupled capacitance. This may cause functional failure of the design and lead to more power consumption. Therefore, it becomes important for the designers to model accurate noise characteristics at the cell level and be aware of the possible failures early in the design cycle. 

Cross Coupled Capacitance 

 Aggressor and Victim

 

What are the components of noise characterization? 

Broadly, there are two models for noise characterization -- Composite Current Source Noise (CCSN) and Effective Current Source Model (ECSM).

CCSN characterization refers to current-based modeling of accurate noise analysis done using SPICE simulations. The noise information in a Liberty file can be modeled broadly based on the following three components:

  1. DC current table
  2. Timing information of Channel Connected Blocks (CCBs)
  3. Noise propagation information

How is CCSN characterization done in Liberate?

Liberate handles the three main noise components as described below:

  1. DC current table: Input and output of the stage are both connected to a voltage source and each source is varied from -VDD to +2VDD. In addition, the current passing through the output voltage source is recorded and presented in the usual 29x29 table.
  2. CCSN output voltage: Each of the stages is simulated with varying input slews and output loads. Then, the voltage at the output stage is measured at five time points when the output voltage waveform crosses 10%, 30%, 50%, 70% and 90% of maximum rail voltage.
  3. Propagated noise: Symmetric triangular waveforms are used to characterize noise propagation information. Few samples in the 3D space constituted by the three independent parameters – noise height, width and load capacitance –  are needed for simulation.

In Liberate, the noise data is modeled in the following two ways:

  1. Stage-based modeling where the noise data is populated under the ccsn_first_stage and ccsn_last_stage groups.
  2. Reference-based modeling where the noise data is populated under the input_ccb and output_ccb groups.

Also, the CCSN data is stored either under a timing arc or pin. Arc-based storage applies to simple cells like INV and AND where generally the path length is up to 2, whereas pin-based storage is for complex cells with multiple stages.

 

The picture below shows how the noise characterization and modeling methodology is handled by Liberate at different stages.

 

What are the advantages of using Liberate for CCSN characterization?

Liberate offers the following advantages for CCSN characterization:

  • Automatic identification of the CCB and automatic vector generation for those.
  • High level of simulation accuracy and ultra fast speed using Spectre APS engine.
  • Highly parallelized job distribution to improve turnaround time.
  • Support available for both old and new formats of CCSN characterization and modeling.
  • Added functionality to validate the noise data (structurally as well as numerically) using the check_ccsn utility that is integrated in the tool.
  • User has full control over noise characterization that is made available through specific parameters.

What next?

Once we have cell-level noise data comprising the CCS Noise or Effective Current Source Model (ECSM) Noise libraries from Liberate, this data is used by downstream tools to analyze the effects of glitches on bigger blocks or designs. Several models like Receiver Input Peak (RIP) and Receiver Output Peak (ROP) are used for noise analysis that in turn uses Voltage-in/Voltage-out tables for the first and last stages of every cell timing arc from Liberty files for quick and accurate glitch study.

With this, I'll bring this blog to an end, leaving a trailing thought for you about how do you think noise can pose characterization and design challenges in advance nodes? 

Until I return with more, take care!

Signing off for now.

~Moinak Gorai

   

Related Resources

   Troubleshooting Article

How to model CCSN in input_ccb/output_ccb formats

  Product Manual

Liberate Characterization Reference Manual

Liberate Characterization Portfolio Command and Parameter Support Matrix

Contact Us

For any questions, general feedback, or even if you want to suggest a future blog topic, write to liberate_rm@cadence.com. 

    About Library Characterization Tidbits

    Library Characterization Tidbits is a blog series aimed at providing insight into the useful software and documentation enhancements in the LIBERATE release. In addition, this series would broadcast the voices of different bloggers and experts, who would share their knowledge and experience about all the tools in Liberate Characterization Portfolio. To receive notifications about the new blogs in this series, click Subscribe and submit your email ID in the Subscriptions box.

     


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