Library Characterization Tidbits: The Perfect Solution for Validating Libraries

Creation of library views is a complex process because these contain the electrical information that is used throughout design implementation, starting from logic synthesis through design optimization to the final signoff verification. The process involves multiple circuit simulations, data measurements, and model transformations, which are typically distributed across a large computer network. In such a complex process, there is a high probability of introducing errors. The reasons for errors include network failures, simulation convergence problems, optimistic characterization assumptions, software version incompatibilities, measurement inaccuracies, and incorrect user inputs.

As each set of libraries is used for multiple chip designs, it is paramount that the library data is complete and correct. The Cadence^® Liberate^TM LV library validation solution provides a collection of capabilities to validate and verify each library to ensure data consistency, accuracy, and completeness.

You can perform extensive and efficient library validation using the following Liberate LV commands:

• compare_library
• compare_structure
• validate_library

Let us look at the various requirements due to which you will need to validate your libraries.

Consistency in Library Data

Liberate LV provides several data consistency checks, such as comparing table-based delay data against current (Composite Current Source) data, checking for non-monotonic delays, and incorrect values such as negative values in rising current waveforms.

Library Revisions

There may be situations when you want to check a new library against an existing library, to identify changes in function, delay, power, and noise immunity between the two libraries. Liberate LV provides the means to compare the two libraries and generates both graphical and text reports along with the comparison data.

Accuracy of Library Data

Liberate LV compares the library models in the appropriate static timing analysis tools against the results obtained from transistor-level circuit simulations. To ensure timing accuracy, Liberate LV invokes a static timing analyzer and compares the resulting values against the simulations of the test circuit using a SPICE simulator. Test circuits are automatically created for each check.

These critical requirements are taken care of by the Liberate LV solution, ensuring that you get excellent validation results.

That’s all I had for you in this blog. I will be back with more blogs on the Cadence characterization products.

- Helen Shi

Related Resources

About Library Characterization Tidbits

Library Characterization Tidbits is a blog series aimed at providing insight into the useful software and documentation enhancements in the LIBERATE release. In addition, this series would broadcast the voices of different bloggers and experts, who would share their knowledge and experience about all the tools in Liberate Characterization Portfolio. To receive notifications about the new blogs in this series, click Subscribe and submit your email ID in the Subscriptions box.