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VoltusTM IC Power Integrity Solution is a power integrity and analysis signoff solution that is integrated with the full suite of design implementation and signoff tools of Cadence to deliver the industry’s fastest design closure flow. The aim of this blog series is to broadcast the voices of different experts on how design engineers can effectively use the diverse Voltus technologies to achieve high-performance, accuracy, and capacity for next-gen chip designs.
This blog is in continuation to the previous blog post on the IR-Aware placement technology used at the early design stage to mitigate IR drop hotspots, prevent multiple signoff iterations, and achieve faster design closure. In Part 2 of this blog post, continuing with the spirit of “a stitch in time saves nine”, we underline the importance of tying any loose ends at every stage and every stitch that goes into the digital IC design flow. This is where Innovus PI’s pattern-based power-ground (PG) stripes addition comes into the picture—a technology that enables design engineers to localize and remove the remaining hotspots.
Design engineers often struggle in the tradeoff between the robustness of the power-grid and availability of routing resources. A robust design could address the IR drop issues but drastically reduce the routing resources, causing congestion issues. Consequently, there has been a need to slightly under-design the power-grid and fix the remaining violations only on the relevant areas in the design, restricting the fix to specific metal layers. This is precisely the reason for adding local PG metal stripes or vias.
While the cell-spreading technique applied in the Current Density-Based IR-Aware Placement flow has made it possible to address most of the violations, it simply cannot address the violations occurring in the following scenarios:
The following picture shows a hotspot spanning several vertical stripes:
A new technology has come in handy to overcome the above shortfalls. Pattern-based PG Addition or Power-Grid Reinforcement is a power-grid optimization technique that accepts one or more PG patterns as the input and applies them on each tile of the design that contains violations. The user-defined PG pattern specifies the pattern to be used for IR drop fixing, defining attributes such as the metal layer, metal width, spacing, maximum distance between the generated stripes, and so on.
The IR-Aware Full Flow solution first uses VoltusTM IC Power Integrity Solution to perform IR drop analysis and divide the design into tiles, identifying and marking those tiles with violations. Subsequently, it uses InnovusTM Implementation System to add these user-defined PG patterns while avoiding creation of new design rule checks (DRCs).
PG pattern definition is very important to achieve optimal IR drop gain. The purpose of adding more stripes is to reduce the cell instance resistance that restricts the flow of current towards the voltage supply. For this reason, it is important to first understand where the existing grid has the maximum resistance, or better, where this resistance is causing the highest IR drop. To do this, the design engineers can easily leverage the generated Resistance of Least Resistive Path (RLRP) report to identify the optimal layer and net for fixing among those that are contributing more to the total cumulative IR drop.
In the following RLRP report generated for a 7nm design, you can see that the IR drop for the VDD and VSS nets is highest between metal layers M10 and M0:
For this design, the violations were fixed by creating a simple pattern for M5 with stacked vias up to M10 and down to M0, thereby resulting in an IR drop improvement for VDD and VSS.
Another example would be of a design where most of the IR drop is between M3 and M9. Here, the existing power-grid and routing permits the addition of stripes in the M3/M5/M9 layers, so we can add either M3-to-M5 pattern or M5-to-M9 pattern, or both.
The following example is a comparative analysis of the results for a zoomed-in hotspot area:
After fix + timing optimization
Number of Violations (> 30mV)
Worst local IR Drop
In this design, several standard cells were first moved by the Current Density-Based IR-Aware placement technology, and then the remaining violations were fixed almost completely by locally adding new stripes.
This flow can be used at any of the implementation stages. However, if you intend to add a minimal number of stripes to the design, it is recommended to do so after the CTS stage when the IR drop is more stable because the clock structure is fixed. The multiple possibilities offered by this placement and routing refinement flow, such as preservation of the existing clock/signal routing and ability to select specific hotspot regions or specific IR drop thresholds, make this flow suitable for any fixing scenario required by the engineer.
With Innovus PI, designers can leverage multiple optimization technologies, such as early rail analysis on an incomplete P&R design, IR-aware CTS, IR-aware placement and power-grid reinforcement, to address the IR-drop induced design failures and costly late design re-spins. A robust technology indeed that ensures our design has timely guidance and course correction, like the proverbial stitch-in-time, to emerge as flawless as possible.
- Andrea Barletta
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“Voltus Voice” showcases our product capabilities and features, and how they empower engineers to meet time-to-market goals for the complex, advanced-node SoCs that are designed for next-gen smart devices. In this monthly blog series, we also share important news, developments, and updates from the Voltus space.
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