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VoltusTM IC Power Integrity Solution is a power integrity and analysis signoff solution that is integrated with the full suite of design implementation and signoff tools of Cadence to deliver the industry’s fastest design closure flow. The aim of this blog series is to broadcast the voices of different experts on how design engineers can effectively use the diverse Voltus technologies to achieve high-performance, accuracy, and capacity for next-gen chip designs.
“A stitch in time saves nine” is an idiom with universal appeal and one that stresses on the importance of how early pre-emptive action and planning can prevent a problem from aggravating and causing irreversible damages at a later stage. The digital IC design flow is a case in point. It is imperative to anticipate and refine the design flow through all the steps—from floorplanning to signoff—to save precious time and development costs that a fix-it-at-signoff approach will probably generate.
We are all aware that IR drop and electromigration take centerstage when it comes to power integrity issues. These two interrelated issues cause functionality failure in electronic devices, especially with lower technology nodes where more performance needs to be extracted from a smaller area. One of the main goals of a power integrity analysis solution is to detect “hotspots” or IR drop exceeding a threshold on the chip as early as possible to prevent degradation of chip performance.
The traditional power integrity solutions tend to kick in at the signoff step, but they do not deliver the accuracy or speed required to keep up with the demands of the advanced SoCs. The primary reason for this is insufficient analysis during the early design stages. If there are power integrity violations identified at the signoff stage, it would result in long iterative feedback loops back to the implementation stage to fix these violations after the designs are completed. This flaw can be corrected with a power integrity solution that eradicates the need for the design engineer to retreat to a previous implementation phase, and instead, applies a convergence methodology that accounts for power integrity at each step of the physical design flow.
Integration between Cadence® VoltusTM IC Power Integrity Solution and InnovusTM Implementation System provides design engineers with a unique solution called Innovus Power Integrity (also known as IR-Aware Full Flow) to enable the interaction between the Place & Route (P&R) implementation and IR drop analysis signoff steps. This approach pulls the potential power signoff issues ahead into the design implementation stage, thereby allowing early feedback, prevention and fixing, avoiding various difficult and costly design fixes or changes at the signoff stage.
The following are some of the IR drop-centric technologies enabled by Innovus Power Integrity that help to achieve the voltage drop requirements:
In this two-part blog, we will focus on the IR drop-aware placement technology. The IR drop-aware placement flow mitigates IR drop hotspots by spreading the simultaneous switching aggressors to different locations, reducing the local current requirements and the IR drop. This flow has the following two modes that can be used at any stage in the flow after detail placement:
The following diagram illustrates how local IR drop (in red) is reduced when some cells are moved and supplied by another power rail:
For a 7nm high speed processor design with a 3GHz clock speed, the following IR drop distribution table shows the results before and after fixing (IR aware placement):
The following example shows comparative analysis of the results for a zoomed-in hotspot area before and after the current density-based IR-aware placement flow:
Before IR-Aware Placement
After IR-Aware Placement
Number of Violations
Worst Local IR Drop
IR Drop Distribution on the Whole Design
The following are the advantages of the IR-aware full flow:
Although substantial cell padding can be applied and high IR drop contributors can be displaced from each other, with neighboring cells also distanced from the contributors, violations could still persist. Additional padding may help but won’t resolve the self-induced IR drop. The second part of this blog will discuss how the remaining violations can be fixed completely by adding local PG stripe/via.IR-Aware placement is hence an integral step in this tightly coupled solution to alleviate signoff bottlenecks and provide faster convergence at the end of the flow. This little "stitch in time" can go a long way in eliminating the possibility of an all-out rip off!
- Andrea Barletta
For more information on Cadence digital design and signoff products and services, visit www.cadence.com.
“Voltus Voice” showcases our product capabilities and features, and how they empower engineers to meet time-to-market goals for the complex, advanced-node SoCs that are designed for next-gen smart devices. In this monthly blog series, we also share important news, developments, and updates from the Voltus space.
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