Voltus^TM IC Power Integrity Solution is a power integrity and analysis signoff solution that is integrated with the full suite of design implementation and signoff tools of Cadence to deliver the industry’s fastest design closure flow. The aim of this blog series is to broadcast the voices of different experts on how design engineers can effectively use the diverse Voltus technologies to achieve high-performance, accuracy, and capacity for next-gen chip designs. Stay tuned for our monthly posts on every third Wednesday.    

Back in the day, before the pandemic started, my mornings were so hectic. It often felt like a race against the clock. The frantic rush—to drop off the kids, to make it in time for the office meeting, or a school event—seems to be part of a distant past now. While trying to accomplish the morning chores, I remember how getting my hair in order would drain my precious morning time, particularly in winter. Haven’t you experienced your hair becoming a disorderly mess each time you run a nylon brush through it, or seen your clothes cling together refusing to accept the look you intended, or felt the sudden unpleasant shocks from your car door handle?

These inconveniences are caused by static electricity. As we know, all objects may carry positive and negative electrical charges. Static electricity is generated when an imbalance of electrical charges exists within an object—like the brush in the above example. When this imbalance attains a significant potential difference, there is a sudden and instantaneous flow of current to another object either through direct contact or through air. This phenomenon is called electrostatic discharge (ESD).

Background of ESD in the Semiconductor Industry

In the semiconductor industry, if this current discharge happens through electronic components, it creates a hair-raising scenario for the design engineer. Especially in modern ICs, problems associated with ESD and yield losses become significant. The thinner gate oxide and shallow junction depth used in advanced-node design technologies make them more susceptible to ESD damages. Normally, the electrostatic discharge can be a few kilovolts but even a small discharge can completely ruin the sensitive IC.

ESD events occur throughout a product’s lifecycle when it is processed by multiple equipment and handled by humans from the factory to the field. Failure in managing the ESD discharge can prove to be disastrous to the internal circuits, which can, in turn, lead to circuit failure. ESD damage can be reduced in the following two ways:

• Grounding of any equipment and humans involved in handling the IC.
• Designing a suitable ESD protection circuit that provides a discharge path to the rushing current before it reaches damaging levels.

How Voltus Minimizes Vulnerability to ESD

Voltus offers an efficient solution for the analysis and optimization of your ESD protection circuitry. Instead of waiting till the final ESD signoff, you can now run ESD analysis during the floorplan stage and check if your ESD network meets the resistance requirements from the foundry. The solution encompasses a massively parallel architecture that offers improved memory footprint, performance, and scalability.

The ESD analysis flow is run on IC designs to check whether every power and ground pin or bump has an ESD device, and the device is placed in such a way that it does not violate the effective resistance or current density limit.  The flow enables you to perform the following checks for ESD discharging paths across multiple diodes or clamps:

• bump-to-clamp effective resistance
  
• bump-to-bump effective resistance
  
• clamp-to-clamp effective resistance
  
• isolated bumps (bumps not protected by any ESD device)
• isolated clamps (floating ESD devices)
• current density
  

Such information tells design engineers if there are any violations caused by the high effective resistance or if the current density is above the threshold value.

Voltus also performs analysis of charged-device model (CDM) based ESD events that occur when a chip is charged during manufacturing, for example, when the chip encounters a conductive surface during board assembly. Using these methods, engineers can seamlessly determine whether more ESD protection is required in the ESD circuit. Moreover, calculating the effective resistance between a large number of nodes is a difficult engineering problem, burdened with large design and computational complexity. The traditional graph-based search algorithms can only identify the least resistance or shortest paths. This type of analysis is error-prone because the current discharge can occur in paths other than the shortest paths. The Voltus solution enables designers to obtain a global view of the power grid to determine all the possible discharge paths and achieve a high-capacity analysis solution without over-designing ESD protection.

The Benefits of ESD Checks Using Voltus During Full-Chip Analysis

The Voltus ESD Analysis solution enables easy identification of ESD issues to implement an effective protection scheme through the following key differentiators:

Now, if you are wondering how to perform ESD analysis for your designs, the "Demystifying ESD" series will take you through a range of topics like the different types of ESD checks, how to read and analyze ESD reports, and best practices for running ESD for large designs. Watch out for our future posts in this series that will guide you in designing products with better resistance to electrostatic discharge events.

So, get ready for the Voltus experience and leave all those hair-raising incidents behind.

Vijetha K Singh

Related Resources

 Performing Electrostatic Discharge Analysis in Voltus

About Voltus Voice

“Voltus Voice” showcases our product capabilities and features, and how they empower engineers to meet time-to-market goals for the complex, advanced-node SoCs that are designed for next-gen smart devices. In this monthly blog series, we also share important news, developments, and updates from the Voltus space.

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