Voltus^TM IC Power Integrity Solution is a power integrity and analysis signoff solution that is integrated with the full suite of design implementation and signoff tools of Cadence to deliver the industry’s fastest design closure flow. The aim of this blog series is to broadcast the voices of different experts on how design engineers can effectively use the diverse Voltus technologies to achieve high-performance, accuracy, and capacity for next-gen chip designs.

Can we compare Resistance Analysis to the management of an airport? Yes, we can because they are both strategies that seek to reduce any impediment to the flow of their subjects through a complex grid. The major challenge in designing a modern airport is getting passengers from the entry, through check-in, security check, customs clearance, and onward to the door of the aircraft in the shortest possible time. It is pertinent to remove any obstacles that will restrict or block their progress to the exit gates, and if they do linger, they get diverted to the food court or duty-free shopping sections, but every minute they spend in the airport complex means more energy is used up in keeping them warm or cool, hydrated and entertained. That’s quite like the chip we design that envisages electron flow through a grid but with minimal resistance that could lead to heating and chip failure.

The Necessity of Resistance Analysis for Your IC

With innovations in advanced process technologies and ever-growing power densities, the interconnect wire width continues to become thinner. This leads to an increase in the wire resistance and therefore in the amount of voltage drop in the chip. The risk of chip failure due to excessive voltage drop is on rise, which is triggering power-integrity convergence issues. A sign of these failures is the declining rate of first-time silicon success and the increasing number of design iterations required in manufacturing digital IC designs. The voltage loss in your design can be attributed to the following metrics:

• Tap currents from the standard cells, memories, and IPs
• Resistivity of the power grid network

Foundries provide the IR drop thresholds and the corners to be used for IR drop analysis with the intent of obtaining the power grid signoff by eliminating any design surprises before they reach the foundry. The Voltus resistance analysis flow leverages this information to determine the weak spots in the power-rail design that are to be addressed by a design team.

Different Resistance Analysis Techniques

There’s no such thing as one-size-fits-all when it comes to resistance analysis. Here are the three types of resistance analysis techniques that can be considered to prevent a voltage drop and model a robust power grid.

Full-chip Resistance Analysis

Full-chip resistance analysis calculates the effective resistance between all the instances to all the voltage sources in a cell-based design. This technique is used when you have huge IR drops in different locations of a design,  and want to verify if the voltage drop is due to either the grid resistivity weakness or power consumption of the design.

The effective resistance calculation flow can be run with the report_resistance command. The following is an example of the full-chip resistance analysis for power net VDD:
report_resistance -net_name VDD -output_dir effr_VDD

In this case, Voltus generates a text report (effr_VDD/VDD_110C_reff_1/REFF/effr.rpt) showing the effective resistance (REFF) of instances sorted from high to low:

The report is sorted by the effective resistance, the REFF value, so that the cell instances impacted by the huge mesh resistivity can easily be seen. Those cells are candidates for large IR drop issues. A GIF file that allows you to quickly see the location of the weak spots is also created in the same directory.

Point-to-Point Analysis

This technique involves the calculation of the effective resistance between the specified node pairs or instance pairs. The point-to-point resistance analysis flow ignores all voltage sources. This analysis technique can be used to check specific IP resistivity rules, for example, a pin or XY coordinate in an IP should be at a REFF less than the threshold.

The following is an example of point-to-point resistance analysis for ground net VSS:
report_resistance -net_name VSS -node_pair_list {335 391 M5 335 367 M5}

In this case, Voltus generates a report (effr_VDD/VDD_110C_reff_1/REFF/effr.rpt) showing the effective resistance (REFF) for a given pair of nodes and the corresponding path (X1/Y1/LAYER1  to  X2/Y2/LAYER2):

Least-Resistance Path (RLRP) Analysis

The least-resistance path (RLRP) analysis technique calculates the total resistance between an instance and its voltage source along the least-resistive path. If the instance has multiple power pins connected to the power grid, the worst resistance path is selected to plot the instance data. This technique is often used to see the voltage drop on a specific instance, and thereafter, check its resistor path to the bumps/pads for a detailed analysis of the worst (highest) resistance.

You can run the RLRP analysis using the following command:
set_rail_analysis_config -enable_rlrp_analysis true

To find out the root cause of resistance, you can use the RLRP path display. This feature will highlight the least resistance path for VDD and VSS between the selected instance pins and their closest voltage source. The figure below shows how the RLRP of an instance appears on the layout:

In this example, the instances far from the stripes have an important resistance penalty because the only path to reach the stripe is the long metal1 layer. Two different colors are used here, one for VDD and one for VSS. The Resistance Path form (GUI report) on the right displays the details for each segment of the path—it gives the layer and coordinates, resistance value, cumulative resistance value from the source point, voltage drop, and cumulative voltage drop. When looking at the different rows in this form, you may see a big jump in the resistance value of certain segments due to a poor via connection or a very long metal shape.

In summary, the Voltus Resistance Analysis feature offers a comprehensive solution to identify the potential sources of power grid design problems, and improves the reliability of the power grid before the signoff stage. Now that you have taken the path of least resistance, let’s stop worrying about it and enjoy the airport lounge before our next flight!

Related Resources

For more information on Cadence digital design and signoff products and services, visit www.cadence.com/go/voltushs.

About Voltus Voice

“Voltus Voice” showcases our product capabilities and features, and how they empower engineers to meet time-to-market goals for the complex, advanced-node SoCs that are designed for next-gen smart devices. In this monthly blog series, we also share important news, developments, and updates from the Voltus space.

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