Voltus^TM IC Power Integrity Solution is a power integrity and analysis signoff solution that is integrated with the full suite of design implementation and signoff tools of Cadence to deliver the industry’s fastest design closure flow. The aim of this blog series is to broadcast the voices of different experts on how design engineers can effectively use the diverse Voltus technologies to achieve high-performance, accuracy, and capacity for next-gen chip designs.

One of the major challenges for chip power integrity (PI) analysis is the size of the power and ground networks. Simulating these huge networks requires solvers with very high performance and capacity. With the advent of larger AI and hyperscale designs, this problem has become even more complex. Data shared by some of our customers shows an exponential trend in compute resource requirements, thereby adding massively to the cost of performing PI analysis. Power signoff engineers must now deal not only with PI issues, but the demands for these resources as well.

Another challenge in PI analysis is that power networks are meshes that are strongly coupled, especially when the analysis includes package models. Any voltage or current variation in one part of the design will have an impact on other areas of the power and ground network. This has been a challenging issue for a divide-and-conquer or hierarchical approach. To achieve optimal accuracy, any such hierarchical solution would need to preserve the electrical properties and the demand current of the whole network.

Voltus XM Steps Up the Game!

Anticipating these challenges and aided with feedback from some of our leading customers, the Voltus development team now has a hierarchical solution--Voltus Extreme Modeling (XM)--that can significantly cut down on compute resource requirements and achieve very high accuracy. The maximum difference between running a full flat analysis versus hierarchical analysis with Voltus XM is just 1% without package models and within 5% with package models. Voltus XM is already being used by some of our leading customers who now benefit from this breakthrough technology, with more than 50% reduction in CPU and memory requirements.

Here are some advantages of using Voltus XM:

- Delivers an accurate signoff solution both at the full-chip and sub-chip levels for extremely large designs

- Offers a fully coupled and accurate model-based hierarchical solution

- Breaks the exponential trend of ever-increasing memory and CPU requirements

- Builds compact IP models that help perform faster analysis with much less memory

- Provides very good correlation with fully flat analysis

The Voltus XM Design Flow: Hierarchical PI Analysis on a Grand Scale

The Voltus XM solution enables designers to run hierarchical PI analysis using IP modeling technology to create reduced power-grid models of the IP blocks, accurately capturing the demand current and electrical parasitics.  Voltus XM has a very simplified use model to aid designers as they move from early to signoff analysis. Running this model-based hierarchical EM-IR analysis flow requires two steps:

1. Build the IP models referred to as xPGV
2. Add the xPGV models in the analysis

What is especially remarkable about Voltus XM is that the block-level xPGVs can be context-independent, relying solely on the block-level information, while the top-level analysis still produces very accurate results no matter where they are placed or how many times they are instantiated.  The XM solution enables engineers to create xPGV models for specific IP blocks that require analysis, without having to simulate the surrounding blocks of large designs.

Case Study: Result Comparison of a Full Flat vs XM Analysis Flow for a 7nm Design

In the XM flow, we generated xPGVs for three blocks (A, B, and C). The three xPGVs along with the flat top-level were used for the top-level logic and grid analysis. The results show that there is significant reduction in the number of power grid nodes, memory and runtime using the same number of CPUs.

With its easy-to-implement and cost-effective methodology, Voltus XM introduces a new paradigm for performing on-chip PI analysis that reduces compute resource requirements on extremely large design projects.

In the next post of the Voltus XM blog series, we will take a deep dive into generating xPGV models and then validating the static/dynamic tap currents in these models.

Related Resources

For more information on Cadence digital design and signoff products and services, visit www.cadence.com/go/voltushs.

About Voltus Voice

“Voltus Voice” showcases our product capabilities and features, and how they empower engineers to meet time-to-market goals for the complex, advanced-node SoCs that are designed for next-gen smart devices. In this monthly blog series, we also share important news, developments, and updates from the Voltus space.

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