Voltus^TM IC Power Integrity Solution is a power integrity and analysis signoff solution that is integrated with the full suite of design implementation and signoff tools of Cadence to deliver the industry’s fastest design closure flow. The aim of this blog series is to broadcast the voices of different experts on how design engineers can effectively use the diverse Voltus technologies to achieve high-performance, accuracy, and capacity for next-gen chip designs.

Smartphones have become ubiquitous and essential in our fast-paced lives. From talking to our loved ones to using them for grocery shopping to responding to work emails, these devices have now become the first object we seek on waking up every morning. You sometimes discover with horror that there isn’t enough power to take an important call and while rushing to plug it, you wonder how the battery discharged so quickly… well you’re not alone. New-age smartphones boast of compact size, numerous apps and glitzy HD displays, but are very thirsty when it comes to battery power. Our engineers’ challenge when designing chipsets in these pocket devices is to meet the power demands that the circuit craves while preventing overheating and battery drainage.

Power dissipation in a digital circuit is primarily due to dynamic power (switching of active devices) and static power (leakage of inactive devices). Among the many low-power techniques, clock gating and power gating are two of the most effective techniques to reduce dynamic and leakage power, respectively. In this blog, we discuss power-gating analysis, a technique to address the design challenge of extending battery life while reducing the leakage or “static” power. With power gating, a multitude of functionalities are dynamically sequenced in unique combinations for enabling (powering-up) or disabling (powering-down) blocks within ICs. Disabling select blocks results in shutting off the power supply to them for a specific interval of time, leading to substantial power saving. For example, if a smartphone has a video player function but no video is being viewed, it makes sense to power-down that block.

The Importance of Power-Gating Analysis for Advanced Chip Performance

A little more information on the power-gating analysis, also known as “power-up analysis”, will help you appreciate the importance of this silicon power-saving technique. In a traditional design flow, the different types of analyses - such as static or dynamic timing analysis, power analysis, and IR drop analysis - are performed in the steady-state mode. This means the power supply voltage has reached a threshold, say 95% of the battery voltage, and is stable so that the functioning of the chip can be initiated. Yet a lot could happen during the transition from the off state to the stable/active state of power supply if power-up implementation is not analyzed properly. For example, some functional blocks may take more time to boot up, or a particular block may drain the battery faster than the surrounding blocks. The improved battery life of some devices over others can be attributed to implementation of the powering-up techniques efficiently and correctly.

One of the most important considerations for power-gating analysis is to identify and regulate the rush of currents when powering-up several blocks. This can be done by controlling the firing sequence of the power switches/gates that turn off power supply to these blocks. In a circuit with multiple power domains (blocks with the same supply voltage), the switched power domain is connected to the always-on power domain through power gates. This is done to dynamically turn a part of the chip ON/OFF.

The design objective is to achieve the shortest possible turn-on time of the switched-domain without exceeding the rush current. The rush current can be computed using the following simple equation:

I=C.dV/dT

Per the equation, the peak rush current can be controlled either by guiding the capacitance ‘C’ of the switched power domain or the ramp-up rate of the supply voltage. Reducing capacitance means either optimizing the design for the gate count or moving to the lower process nodes. Voltage ramp-up rate can be controlled using voltage regulators (VRM) or built-in circuits within power switches. A combination of these adjustments can help maintain a balance between the peak rush current and ramp-up time.

How does Voltus Intervene in this Scenario?

Voltus^TM IC Power Integrity Solution can help at three levels:

• Analyze multiple functional blocks in different states simultaneously, as shown in the following figure, where one block is powering-up, two are in the steady state ‘ON’ condition, and one is shut off.
  
• Plot and review the rush current drawn by the switched power domain for each switch and powering-up rail.
  
• Analyze the design and report the rush current value, turn-on time, and failure of a power switch exceeding its saturation current limits.

Since Voltus is integrated with Cadence Innovus^TM Implementation System, design engineers have the unique capability to simultaneously perform low-power analysis and make design-level changes. Voltus also supports both industry-standard power intent formats CPF and IEEE 1801, enabling design teams to adopt the flow of their choice. Our power-gating solution allows engineers to optimize the current flow in the design by recommending the ideal number and placement of the power-gating switches in the circuitry. Such a solution can help achieve an optimal trade-off between power and performance targets of battery-operated devices, providing more functionality with less power.

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About Voltus Voice

“Voltus Voice” showcases our product capabilities and features, and how they empower engineers to meet time-to-market goals for the complex, advanced-node SoCs that are designed for next-gen smart devices. In this monthly blog series, we also share important news, developments, and updates from the Voltus space.

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