Voltus^TM IC Power Integrity Solution is a power integrity and analysis signoff solution that is integrated with the full suite of design implementation and signoff tools of Cadence to deliver the industry’s fastest design closure flow. The aim of this blog series is to broadcast the voices of different experts on how design engineers can effectively use the diverse Voltus technologies to achieve high-performance, accuracy, and capacity for next-gen chip designs.

Have you ever found yourself searching for a treasured vacation picture or a work document on your machine, but are unable to trace it because you can’t remember the file name, its location, or when it was created? Finding that wayward file is like looking for a needle in a haystack. We have all tried to dig out that one file from amongst thousands and a few lucky ones may have had that Aha! moment of finally finding it after a long, frantic, and anxiety-ridden search. When it comes to accurately predicting probable paths for timing violations among 200,000+ static timing analysis (STA) paths, however, you may not be so lucky!

What’s Changed with Smaller Process Geometries Impacting IR Drop

Of all the challenges of electrical signoff, performance degradation and chip failures remain the most complicated despite passing the timing and IR drop signoff verification checks. Starting from 28nm down to 5nm, the following process technology changes occur:

• Increase in interconnect resistance (more than ten times!) of the layers
• Transient IR drop (∆V) that is larger in magnitude with longer recovery time
• Cell delays that are increasingly sensitive to IR drop

The “timing closure” dilemma for a design engineer is evident. If you increase the IR drop margin, the signoff tool makes a pessimistic estimation by generating extra timing violations and leads to over-design of the power-grid to meet the timing requirements. And with a lesser IR drop margin, the tool fails to detect the IR-sensitive timing paths prior to tapeout. Both these decisions limit the design performance and contribute to silicon failure.

To delve a little more on the IR drop-induced timing failure topic, let us look at it in the context of IR drop applied to the cells on the critical path for timing analysis. The following layout view from a 5nm design shows the IR drop-induced timing failure:

• The green lines stitch together the critical path of the design.
• The cells on the critical path have a 120mV drop (IR threshold of 100mV drop).
• The aggressor or neighboring cells have a 70mV drop.

It is important to note that the cells in proximity of the critical path (IR drop < 70mV) also contribute to the 120mV drop; therefore, the existing localized IR drop may get amplified in realistic conditions. Such cases of local excessive IR drop (thus, the timing impact and potential failures) are not being captured by the traditional signoff methodologies and flows.

True Signoff with Tempus PI

We will explore how Tempus Power Integrity (Tempus PI), a breakthrough technology that integrates Tempus^TM Timing Signoff Solution and Voltus^TM IC Power Integrity Solution, addresses the need for a true signoff solution at advanced nodes, especially for 7nm and below. The Tempus PI technology delivers the next-generation IR drop analysis by identifying the silicon performance failures that were missed by traditional IR analysis.

Timing and voltage drop analyses are interwined - switching times affect the current draw on power rails, and power rail voltages affect cell delays. We are confronted with the classic “chicken or egg” paradox that can only be solved through precise timing-power integration to allow for iterative convergence on realistic rail voltage and timing. Tempus PI performs concurrent timing and power analysis that enables the designer to assess the overall timing impact on IR drop and speeds design closure. This integrated solution is based on the following methodologies:

Identification of Voltage-Sensitive Paths and Aggressors

Tempus PI for True Signoff demands both timing critical path and IR-sensitive path analyses.

The timing critical path analysis is performed using the traditional VDD margins with the assumption that all cells have the same max IR drop applied to them. Subsequently, Tempus PI determines the IR-sensitive paths that are originally not critical paths but can potentially become one in realistic IR conditions. This technology leverages the machine learning techniques to predict paths with voltage-sensitive instances, timing-sensitive instances, and resistance-sensitive voltage aggressors for complete IR drop analysis coverage.

Targeted Vectorless Simulation

Using a vectorless-based activity generation algorithm, Tempus PI adopts a directed and well-thought-out approach to generate the power switching events for the timing critical paths, voltage-sensitive paths, and for the overall design. This solution creates switching scenarios that are realistic and worst-case, not just for the critical paths but for the surrounding environment as well.

Automatic ECO Fixing of Timing and IR Drop Violations

Tempus PI uses various ECO fixing strategies, such as cell swapping, cell and aggressor resizing, and buffer insertion and deletion, to fix violations on both the timing critical and voltage-sensitive paths.

Case Study of a 5nm System-on-Chip Design

For a design with 20 million instances, the following is an analysis of a slack report (data table of timing and number of paths) from the traditional timing signoff flow compared to a slack report from the Tempus PI flow:

The reports indicate that the timing paths that displayed a positive slack in the traditional analysis flow (Signoff STA with Flat 10% Voltage Derate) now show a negative slack in the Tempus PI analysis flow. By identifying an additional 2,092 critical paths that would have been missed by the customer’s traditional IR drop analysis flow, we now have a set of timing paths with accurate cell voltages exposing potential silicon problems.

Tempus PI enhances your ability to measure the actual timing impact of IR drop and averts over-design caused by simplistic across-the-board IR drop limits, so that you can become an expert in finding the failing timing paths in your digital design haystacks. Trust Tempus PI to locate that specific violating path, block out resultant timing failures, and achieve the fastest path to predictable design closure.

- Jerry Zhao

Related Resources

• Cadence Defines a New Signoff Paradigm with Tempus PI
• Addressing the Power Integrity Signoff Crisis with Tempus Power Integrity (Webinar)
• Tempus Power Integrity Flow (Video)

For more information on Cadence digital design and signoff products and services, visit www.cadence.com.

About Voltus Voice

“Voltus Voice” showcases our product capabilities and features, and how they empower engineers to meet time-to-market goals for the complex, advanced-node SoCs that are designed for next-gen smart devices. In this monthly blog series, we also share important news, developments, and updates from the Voltus space.

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