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Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium

Time on Your Side: Launching PSS Perspec Composer

We all agree that time is precious. As PSS ( Portable Stimuli Standard ) models get…

OK202502201742
• 3 min read
featured , Perspec , pss , portable stimulus

Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)

USB Promoter Group has released the eUSB2® Version 2.0 specification (eUSB2v2) in…

Sanjeet Kumar
• less than a min read
Verification IP , eUSB2v2 , featured , Functional Verification , USB
Verification
Latest blogs

Methodology Is Important But Language Matters - Part 2

In this blog, I would like to discuss the direction in the languages that will be…

• 4 min read
High-Level Synthesis , Verification planning and management , TLM-driven design , TLM , System Design and Verification , embedded software , virtual protoype , ESL handoff , SystemC , C-to-Silicon Compiler , TLM 2.0-driven design , verification

An Analogy: UVM Is To OVM As SystemVerilog Is To Verilog

In my last blog entry , I implored Accellera to release UVM 1.0 quickly, standardizing…

• 1 min read
uvm , methodology , Functional Verification , OVM , compatibility , Accellera , OVM 2.1 , VMM

Tech Tip: Easy Way To Re-Run Using The Same Seed

[Team Specman welcomes back Application Engineer Hilmar Van Der Kooij as this week…

• 2 min read
Specman , Funcional Verification , IES-XL

What Does The History of RTL Adoption Foreshadow For The Future of TLM Methodology…

Cadence is in the vanguard of a movement to a higher level of productivity via the…

• 3 min read
TLM , RTL , System Design and Verification , IP re-use , Synthesis , verification

How Big Is An int?

This week I'm taking a break from my series on Android System Verification to talk…

• 8 min read
Small Device C Compiler , wishbone , z80 , OpenCores , ISX

A Look Back On 2009 (Before Hazarding Predictions For 2010)

Before I gaze into a crystal ball and add to the many fine predictions already made…

• 3 min read
SystemVerilog , metric driven verification (MDV) , Functional Verification , C , EDA , e , multi-language , coverage driven verification (CDV) , SystemC , MDV , ESL

Low-Power Verification With SystemC - The Great Unknown

Design teams have used C/C++/SystemC reference models for many years and the trend…

• 1 min read
Functional Verification , CPF , Low-Power , UPF , SystemC , IES , ESL

Why UVM Does Not Equal OVM Plus VMM

In the numerous tweets, blog posts, and online forum discussions on the upcoming…

• 1 min read
uvm , methodology , Functional Verification , OVM , compatibility , Accellera , OVM 2.1 , VMM

Methodology Is Important But Language Matters - Part 1

Historical trends in languagesMany of us have traveled around the world, and while…

• 3 min read
Verification planning and management , TLM , virtual platform , System Design and Verification , ESL High Level Synthesis , OVM , ASIC/ASSP , ANSI-C , C-to-Silicon , virtual prototype , C program , OSCiI , TLM 2.0-driven design , planning and management , ESL

Scalability Made OVM The Ideal Choice For UVM

The popularity of OVM that made it the idea choice for Accellera's UVM is rooted…

• 1 min read
performance , SystemVerilog , uvm , OVM ML , Functional Verification , OVM , e , Simulation acceleration , MDV

Tech Tip: Waving Specman Objects in SimVision

Did you know that you can wave Specman objects in IES-XL *and* also save the wave…

• 1 min read
Specman , debug , Functional Verification , simvision , e , IES-XL

Q&A With Nick Heaton: Accelerating Verification Methodology and Tool Adoption

TeamMDV: Have you ever wondered why EDA Vendors don't make it easier for our customers…

• 5 min read
workshops , IPCM , methodology , Verification methodology , metric driven verification (MDV) , Functional Verification , Incisive , Enterprise Manager , Plan and metrics management , MDV

Android System Verification Part 6

Welcome to Part 6 of Android System Verification. It's getting hard to trace back…

• 3 min read
emulator , android , System Design and Verification , system

Changing The "F" in RTFM to "Fantastic"

Talk about unsung -- tech writers just don't get the credit they deserve. They sit…

• 1 min read
Tech Pubs , Functional Verification , Incisive , Kit , IES , IES-XL

AMIQ DVT Maximizes OVM Reuse Via Methodology Compliance

The Open Verification Component (OVC) defined by the official OVM User Guide in the…

• less than a min read
SystemVerilog , uvm , OVM ML , Functional Verification , OVM , OVM SV , Signal Integrity , AMIQ , IES , IES-XL

Back to Work in 2010

It's back to work in 2010. Thanks for all the great feedback in 2009. I plan to continue…

• 2 min read
global warming , System Design and Verification , code offets , linux

Is The Industry Ready For Mainstream Adoption of Higher Abstraction?

I was recently part of an industry wide interview conducted by Clive "Max" Maxfield…

• 1 min read
TLM , System Design and Verification , SystemC

Adam’s Verification Top 10 In '10

I love top 10 lists. Not so much for the drama of the count-down, but for arguments…

• 3 min read
performance , SystemVerilog , Real Value Modeling , OVM ML , Functional Verification , CPF , OVM , OVM e , Incisive , OVM SV , e , Mixed-Signal , Simulation acceleration , SystemC , VHDL , IES , OVM SC

Android System Verification Part 5

In the previous article I introduced the use of Specman for generating sequences…

• 2 min read
GPS , android , System Design and Verification

Formalizing Multilanguage Mixology For e Users

Historically it’s been very common for e users to have to mix other programming languages…

• 4 min read
SystemVerilog , Specman , TLM , methodology , Functional Verification , Cadence VIP portfolio , OVM , VIP , OVM e , C , e , multi-language , SystemC , sequences , ESL , Matlab , IES-XL

Happy Holidays - OVM on The Path to Standardization

I've just heard that the Accellera VIP Technical Subcommittee (TSC) has voted to…

• 1 min read
uvm , methodology , Functional Verification , OVM , Accellera , verification

Imitation Is The Sincerest Form Of Flattery - We Thank You!

Let me start by sharing some recent blog activity showing competitors doing some…

• 2 min read
System Design and Verification , Incisive , Incisive Software Extensions , C-to-Silicon Compiler , ESL

A Holiday Gift For Verification Projects Adopting MDV

Submitted By MDV Team Member – John Nehls Architect and Team Lead for MDV Solutions…

• 3 min read
workshops , metric driven verification (MDV) , Functional Verification , Enterprise Manager , MDV

Are You Playing with a Full Deck?

A professional gambler confidently place bets because she know the odds, but she…

• 2 min read
SystemVerilog , Functional Verification , CPF , OVM , Low-Power , e , SoC

Android System Verification Part 4

Welcome to Part 4 of Android System Verification. If you are just joining make sure…

• 9 min read
android , System Design and Verification , C program

1st Anniversary Of The Team Specman Blog!

Specmaniacs rejoice: today is the 1st anniversary of the launch of this blog!!! To…

• 3 min read
IEEE 1647 , IntelliGen , Specman , Functional Verification , OVM , OVM e , e , CFS Vision , Aspect Oriented Programming , sequences , FOSS , eRM , Incisive Enterprise Simulator (IES) , AOP , OVMWorld , IES-XL

Specman – SimVision Interaction Tips and Tricks

[Team Specman welcomes guest blogger Alex Chudnovsky of Specman R&D] As we are…

• 1 min read
Specman , Functional Verification , simvision

ARM Techcon3 Virtual Classroom

For those that read my September post about ARM Techcon3 in Santa Clara but couldn…

• less than a min read
System Design and Verification , Techcon3 , ARM
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